regfile_ext_tb.vhd (2058B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity regfile_ext_tb is 5 end regfile_ext_tb; 6 7 architecture behav of regfile_ext_tb is 8 9 component regfile_ext is 10 generic ( 11 sz: natural := 4; 12 addrw: natural := 2 13 ); 14 port ( 15 idata: in std_logic_vector(sz-1 downto 0); 16 raddr1: in std_logic_vector(addrw-1 downto 0); 17 raddr2: in std_logic_vector(addrw-1 downto 0); 18 waddr: in std_logic_vector(addrw-1 downto 0); 19 we: in std_logic; 20 clk: in std_logic; 21 rst: in std_logic; 22 odata1: out std_logic_vector(sz-1 downto 0); 23 odata2: out std_logic_vector(sz-1 downto 0) 24 ); 25 end component; 26 27 signal s_sz: natural := 4; 28 signal s_addrw: natural := 2; 29 signal s_idata: std_logic_vector(s_sz-1 downto 0); 30 signal s_raddr1: std_logic_vector(s_addrw-1 downto 0); 31 signal s_raddr2: std_logic_vector(s_addrw-1 downto 0); 32 signal s_waddr: std_logic_vector(s_addrw-1 downto 0); 33 signal s_we: std_logic; 34 signal s_clk: std_logic; 35 signal s_rst: std_logic; 36 signal s_odata1: std_logic_vector(s_sz-1 downto 0); 37 signal s_odata2: std_logic_vector(s_sz-1 downto 0); 38 39 begin 40 uut: regfile_ext port map ( 41 idata => s_idata, 42 raddr1 => s_raddr1, 43 raddr2 => s_raddr2, 44 waddr => s_waddr, 45 we => s_we, 46 clk => s_clk, 47 rst => s_rst, 48 odata1 => s_odata1, 49 odata2 => s_odata2 50 ); 51 52 process begin 53 s_we <= '1'; 54 s_clk <= '0'; 55 s_rst <= '1'; 56 wait for 250 ns; 57 58 s_clk <= '1'; 59 s_rst <= '0'; 60 s_waddr <= "00"; 61 s_idata <= "0101"; 62 wait for 250 ns; 63 64 s_clk <= '0'; 65 wait for 250 ns; 66 67 s_clk <= '1'; 68 s_waddr <= "01"; 69 s_idata <= "1101"; 70 wait for 250 ns; 71 72 s_clk <= '0'; 73 wait for 250 ns; 74 75 s_clk <= '1'; 76 s_rst <= '0'; 77 s_waddr <= "10"; 78 s_idata <= "0010"; 79 wait for 250 ns; 80 81 s_clk <= '0'; 82 wait for 250 ns; 83 84 s_clk <= '1'; 85 s_waddr <= "11"; 86 s_idata <= "1001"; 87 wait for 250 ns; 88 89 s_clk <= '0'; 90 wait for 250 ns; 91 92 s_we <= '0'; 93 s_clk <= '1'; 94 s_raddr1 <= "00"; 95 s_raddr2 <= "10"; 96 wait for 250 ns; 97 98 s_clk <= '0'; 99 wait for 250 ns; 100 101 s_we <= '0'; 102 s_clk <= '1'; 103 s_raddr1 <= "01"; 104 s_raddr2 <= "10"; 105 wait for 250 ns; 106 end process; 107 end behav;