adder32.vhd (624B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity adder32 is port ( 5 a: in std_logic_vector(31 downto 0); 6 b: in std_logic_vector(31 downto 0); 7 cin: in std_logic; 8 s: out std_logic_vector(31 downto 0); 9 cout: out std_logic 10 ); 11 end adder32; 12 13 architecture struct of adder32 is 14 15 component fa is port ( 16 a: in std_logic; 17 b: in std_logic; 18 cin: in std_logic; 19 s: out std_logic; 20 cout: out std_logic 21 ); 22 end component; 23 24 signal y: std_logic_vector(32 downto 0); 25 26 begin 27 y(0) <= cin; 28 cout <= y(32); 29 adder_gen: for i in 0 to 31 generate 30 adder_map: fa port map (a(i), b(i), cin, s(i), cout => y(i+1)); 31 end generate; 32 end struct;