mips.vhd (4122B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity mips is port ( 5 m_clk: in std_logic; 6 m_rst: in std_logic; 7 m_instr: out std_logic_vector(31 downto 0); 8 m_raddr1: out std_logic_vector(4 downto 0); 9 m_raddr2: out std_logic_vector(4 downto 0); 10 m_waddr: out std_logic_vector(4 downto 0); 11 m_reg1: out std_logic_vector(31 downto 0); 12 m_reg2: out std_logic_vector(31 downto 0); 13 m_out: out std_logic_vector(31 downto 0) 14 ); 15 end mips; 16 17 architecture struct of mips is 18 19 component alu is 20 generic ( 21 sz: natural := 32 22 ); 23 port ( 24 alu_in1: in std_logic_vector(sz-1 downto 0); 25 alu_in2: in std_logic_vector(sz-1 downto 0); 26 alu_ctrl: in std_logic_vector(3 downto 0); 27 alu_out: out std_logic_vector(sz-1 downto 0); 28 alu_zero: out std_logic 29 ); 30 end component; 31 32 component regfile_ext is 33 generic ( 34 sz: natural := 32; 35 addrw: natural := 5 36 ); 37 port ( 38 idata: in std_logic_vector(sz-1 downto 0); 39 raddr1: in std_logic_vector(addrw-1 downto 0); 40 raddr2: in std_logic_vector(addrw-1 downto 0); 41 waddr: in std_logic_vector(addrw-1 downto 0); 42 we: in std_logic; 43 clk: in std_logic; 44 rst: in std_logic; 45 odata1: out std_logic_vector(sz-1 downto 0); 46 odata2: out std_logic_vector(sz-1 downto 0) 47 ); 48 end component; 49 50 component instrmem is port ( 51 addr: in std_logic_vector(3 downto 0); 52 c: out std_logic_vector(31 downto 0) 53 ); 54 end component; 55 56 component ctrl is port ( 57 funct: in std_logic_vector(5 downto 0); 58 reg_dst: out std_logic; 59 reg_wr: out std_logic; 60 alu_src: out std_logic; 61 branch: out std_logic; 62 mem_rd: out std_logic; 63 mem_wr: out std_logic; 64 mem_toreg: out std_logic; 65 alu_op: out std_logic_vector(1 downto 0) 66 ); 67 end component; 68 69 component alu_ctrl is port ( 70 funct: in std_logic_vector(5 downto 0); 71 alu_op: in std_logic_vector(1 downto 0); 72 op: out std_logic_vector(3 downto 0) 73 ); 74 end component; 75 76 component pc is port ( 77 clk: in std_logic; 78 rst: in std_logic; 79 ipc: in std_logic_vector(3 downto 0); 80 opc: out std_logic_vector(3 downto 0) 81 ); 82 end component; 83 84 component adder32 is port ( 85 a: in std_logic_vector(31 downto 0); 86 b: in std_logic_vector(31 downto 0); 87 cin: in std_logic; 88 s: out std_logic_vector(31 downto 0); 89 cout: out std_logic 90 ); 91 end component; 92 93 signal s_instr: std_logic_vector(31 downto 0); 94 signal s_op: std_logic_vector(3 downto 0); 95 signal s_alu_out: std_logic_vector(31 downto 0); 96 signal s_alu_zero: std_logic; 97 signal s_reg_out1: std_logic_vector(31 downto 0); 98 signal s_reg_out2: std_logic_vector(31 downto 0); 99 signal s_reg_wr: std_logic; 100 signal s_reg_dst: std_logic; 101 signal s_alu_src: std_logic; 102 signal s_branch: std_logic; 103 signal s_mem_rd: std_logic; 104 signal s_mem_wr: std_logic; 105 signal s_mem_toreg: std_logic; 106 signal s_alu_op: std_logic_vector(1 downto 0); 107 signal s_opc: std_logic_vector(3 downto 0); 108 signal s_adder_to_pc: std_logic_vector(3 downto 0); 109 constant c_pc_add_val: std_logic_vector(3 downto 0) := "0100"; 110 111 begin 112 alu_map: alu port map ( 113 alu_in1 => s_reg_out1, 114 alu_in2 => s_reg_out2, 115 alu_ctrl => s_op, 116 alu_out => s_alu_out, 117 alu_zero => s_alu_zero 118 ); 119 120 regfile_ext_map: regfile_ext port map ( 121 idata => s_alu_out, 122 raddr1 => s_instr(25 downto 21), 123 raddr2 => s_instr(20 downto 16), 124 waddr => s_instr(15 downto 11), 125 we => s_reg_wr, 126 clk => m_clk, 127 rst => m_rst, 128 odata1 => s_reg_out1, 129 odata2 => s_reg_out2 130 ); 131 132 instrmem_map: instrmem port map ( 133 addr => s_opc, 134 c => s_instr 135 ); 136 137 ctrl_map: ctrl port map ( 138 funct => s_instr(31 downto 26), 139 reg_dst => s_reg_dst, 140 reg_wr => s_reg_wr, 141 alu_src => s_alu_src, 142 branch => s_branch, 143 mem_rd => s_mem_rd, 144 mem_wr => s_mem_wr, 145 mem_toreg => s_mem_toreg, 146 alu_op => s_alu_op 147 ); 148 149 alu_ctrl_map: alu_ctrl port map ( 150 funct => s_instr(5 downto 0), 151 alu_op => s_alu_op, 152 op => s_op 153 ); 154 155 156 pc_map: pc port map ( 157 clk => m_clk, 158 rst => m_rst, 159 ipc => s_adder_to_pc, 160 opc => s_opc 161 ); 162 163 adder32_map: adder32 port map ( 164 a => s_opc, 165 b => c_pc_add_val 166 oval => s_adder_to_pc 167 ); 168 169 m_instr <= s_instr; 170 m_raddr1 <= s_instr(25 downto 21); 171 m_raddr2 <= s_instr(20 downto 16); 172 m_waddr <= s_instr(15 downto 11); 173 m_reg1 <= s_reg_out1; 174 m_reg2 <= s_reg_out2; 175 m_out <= s_alu_out; 176 end struct;