pc.vhd (371B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity pc is port ( 5 clk: in std_logic; 6 rst: in std_logic; 7 ipc: in std_logic_vector(3 downto 0); 8 opc: out std_logic_vector(3 downto 0) 9 ); 10 end pc; 11 12 architecture behav of pc is 13 begin 14 process (clk) begin 15 if (rst = '1') then 16 opc <= "0000"; 17 elsif (rising_edge(clk)) then 18 opc <= ipc; 19 end if; 20 end process; 21 end behav;