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reg_tb.vhd (898B)


      1 library ieee;
      2 use ieee.std_logic_1164.all;
      3 
      4 entity reg_tb is
      5 end reg_tb;
      6 
      7 architecture behav of reg_tb is
      8 
      9 signal s_sz:	natural := 4;
     10 signal s_d:	std_logic_vector(s_sz-1 downto 0);
     11 signal s_rst:	std_logic;
     12 signal s_clk:	std_logic;
     13 signal s_q:	std_logic_vector(s_sz-1 downto 0);
     14 
     15 component reg is
     16 generic (
     17 	sz:	natural := 4
     18 );
     19 port (
     20 	d:	in std_logic_vector(sz-1 downto 0);
     21 	rst:	in std_logic;
     22 	clk:	in std_logic;
     23 	q:	out std_logic_vector(sz-1 downto 0)
     24 );
     25 end component;
     26 
     27 begin
     28 	uut: reg port map (
     29 		d => s_d,
     30 		rst => s_rst,
     31 		clk => s_clk,
     32 		q => s_q
     33 	);
     34 
     35 	process begin
     36 		s_rst <= '1';
     37 		s_clk <= '0';
     38 		s_d <= "0010";
     39 		wait for 250 ns;
     40 
     41 		s_clk <= '1';
     42 		wait for 250 ns;
     43 
     44 		s_clk <= '0';
     45 		s_d <= "1110";
     46 		wait for 250 ns;
     47 
     48 		s_clk <= '1';
     49 		wait for 250 ns;
     50 
     51 		s_clk <= '0';
     52 		s_d <= "1010";
     53 		wait for 250 ns;
     54 
     55 		s_rst <= '0';
     56 		s_clk <= '1';
     57 		wait for 250 ns;
     58 	end process;
     59 end behav;