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regfile_tb.vhd (1280B)


      1 library ieee;
      2 use ieee.std_logic_1164.all;
      3 
      4 entity regfile_tb is
      5 end regfile_tb;
      6 
      7 architecture behav of regfile_tb is
      8 
      9 component regfile is
     10 generic (
     11 	sz:	natural := 4;
     12 	addrw:	natural := 3
     13 );
     14 port (
     15 	idata:	in std_logic_vector(sz-1 downto 0);
     16 	addr:	in std_logic_vector(addrw-1 downto 0);
     17 	we:	in std_logic;
     18 	clk:	in std_logic;
     19 	odata:	out std_logic_vector(sz-1 downto 0)
     20 );
     21 end component;
     22 
     23 signal s_sz:	natural := 4;
     24 signal s_addrw:	natural := 3;
     25 signal s_idata:	std_logic_vector(s_sz-1 downto 0);
     26 signal s_addr:	std_logic_vector(s_addrw-1 downto 0);
     27 signal s_we:	std_logic;
     28 signal s_clk:	std_logic;
     29 signal s_odata:	std_logic_vector(s_sz-1 downto 0);
     30 
     31 begin
     32 	uut: regfile port map (
     33 		idata => s_idata,
     34 		addr => s_addr,
     35 		we => s_we,
     36 		clk => s_clk,
     37 		odata => s_odata
     38 	);
     39 
     40 	process begin
     41 		s_we <= '1';
     42 		s_clk <= '0';
     43 		wait for 250 ns;
     44 
     45 		s_clk <= '1';
     46 		s_addr <= "000";
     47 		s_idata <= "0101";
     48 		wait for 250 ns;
     49 
     50 		s_clk <= '0';
     51 		wait for 250 ns;
     52 
     53 		s_clk <= '1';
     54 		s_addr <= "001";
     55 		s_idata <= "1101";
     56 		wait for 250 ns;
     57 
     58 		s_clk <= '0';
     59 		wait for 250 ns;
     60 
     61 		s_clk <= '1';
     62 		s_addr <= "010";
     63 		s_idata <= "0010";
     64 		wait for 250 ns;
     65 
     66 		s_clk <= '0';
     67 		wait for 250 ns;
     68 
     69 		s_clk <= '1';
     70 		s_addr <= "011";
     71 		s_idata <= "1001";
     72 		wait for 250 ns;
     73 	end process;
     74 end behav;
     75