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mips.vhd (3583B)


      1 library ieee;
      2 use ieee.std_logic_1164.all;
      3 
      4 entity mips is port (
      5 	m_clk:		in std_logic;
      6 	m_rst:		in std_logic
      7 );
      8 end mips;
      9 
     10 architecture struct of mips is
     11 
     12 component alu is
     13 generic (
     14 	sz:		natural := 32
     15 );
     16 port (
     17 	alu_in1:	in std_logic_vector(sz-1 downto 0);
     18 	alu_in2:	in std_logic_vector(sz-1 downto 0);
     19 	alu_ctrl:	in std_logic_vector(3 downto 0);
     20 	alu_out:	out std_logic_vector(sz-1 downto 0);
     21 	alu_zero:	out std_logic
     22 );
     23 end component;
     24 
     25 component regfile_ext is
     26 generic (
     27 	sz:		natural := 32;
     28 	addrw:		natural := 5
     29 );
     30 port (
     31 	idata:		in std_logic_vector(sz-1 downto 0);
     32 	raddr1:		in std_logic_vector(addrw-1 downto 0);
     33 	raddr2:		in std_logic_vector(addrw-1 downto 0);
     34 	waddr:		in std_logic_vector(addrw-1 downto 0);
     35 	we:		in std_logic;
     36 	clk:		in std_logic;
     37 	rst:		in std_logic;
     38 	odata1:		out std_logic_vector(sz-1 downto 0);
     39 	odata2:		out std_logic_vector(sz-1 downto 0)
     40 );
     41 end component;
     42 
     43 component instrmem is port (
     44 	addr:		in std_logic_vector(31 downto 0);
     45 	c:		out std_logic_vector(31 downto 0)
     46 );
     47 end component;
     48 
     49 component ctrl is port (
     50 	funct:		in std_logic_vector(5 downto 0);
     51 	reg_dst:	out std_logic;
     52 	reg_wr:		out std_logic;
     53 	alu_src:	out std_logic;
     54 	branch:		out std_logic;
     55 	mem_rd:		out std_logic;
     56 	mem_wr:		out std_logic;
     57 	mem_toreg:	out std_logic;
     58 	alu_op:		out std_logic_vector(1 downto 0)
     59 );
     60 end component;
     61 
     62 component alu_ctrl is port (
     63 	funct:		in std_logic_vector(5 downto 0);
     64 	alu_op:		in std_logic_vector(1 downto 0);
     65 	op:		out std_logic_vector(3 downto 0)
     66 );
     67 end component;
     68 
     69 component adder32 is port (
     70 	x:		in std_logic_vector(31 downto 0);
     71 	y:		in std_logic_vector(31 downto 0);
     72 	z:		out std_logic_vector(31 downto 0)
     73 );
     74 end component;
     75 
     76 component pc is port (
     77 	clk:		in std_logic;
     78 	rst:		in std_logic;
     79 	ipc:		in std_logic_vector(31 downto 0);
     80 	opc:		out std_logic_vector(31 downto 0)
     81 );
     82 end component;
     83 
     84 constant c_pc_add_val:	std_logic_vector(31 downto 0) := x"00000004";
     85 signal s_adder_out:	std_logic_vector(31 downto 0);
     86 signal s_pc_out:	std_logic_vector(31 downto 0);
     87 signal s_alu_out:	std_logic_vector(31 downto 0);
     88 signal s_reg_dst:	std_logic;
     89 signal s_reg_wr:	std_logic;
     90 signal s_alu_src:	std_logic;
     91 signal s_branch:	std_logic;
     92 signal s_mem_rd:	std_logic;
     93 signal s_mem_wr:	std_logic;
     94 signal s_mem_toreg:	std_logic;
     95 signal s_alu_op:	std_logic_vector(1 downto 0);
     96 signal s_op:		std_logic_vector(3 downto 0);
     97 signal s_reg_out1:	std_logic_vector(31 downto 0);
     98 signal s_reg_out2:	std_logic_vector(31 downto 0);
     99 signal s_alu_zero:	std_logic;
    100 signal s_instr:		std_logic_vector(31 downto 0);
    101 
    102 begin
    103 	alu_map: alu port map (
    104 		alu_in1 => s_reg_out1,
    105 		alu_in2 => s_reg_out2,
    106 		alu_ctrl => s_op,
    107 		alu_out => s_alu_out,
    108 		alu_zero => s_alu_zero
    109 	);
    110 
    111 	regfile_ext_map: regfile_ext port map (
    112 		idata => s_alu_out,
    113 		raddr1 => s_instr(25 downto 21),
    114 		raddr2 => s_instr(20 downto 16),
    115 		waddr => s_instr(15 downto 11),
    116 		we => s_reg_wr,
    117 		clk => m_clk,
    118 		rst => m_rst,
    119 		odata1 => s_reg_out1,
    120 		odata2 => s_reg_out2
    121 	);
    122 
    123 	instrmem_map: instrmem port map (
    124 		addr => s_pc_out,
    125 		c => s_instr
    126 	);
    127 	
    128 	ctrl_map: ctrl port map (
    129 		funct => s_instr(31 downto 26),
    130 		reg_dst => s_reg_dst,
    131 		reg_wr => s_reg_wr,
    132 		alu_src => s_alu_src,
    133 		branch => s_branch,
    134 		mem_rd => s_mem_rd,
    135 		mem_wr => s_mem_wr,
    136 		mem_toreg => s_mem_toreg,
    137 		alu_op => s_alu_op
    138 	);
    139 
    140 	alu_ctrl_map: alu_ctrl port map (
    141 		funct => s_instr(5 downto 0),
    142 		alu_op => s_alu_op,
    143 		op => s_op
    144 	);
    145 
    146 	adder32_map: adder32 port map (
    147 		x => s_pc_out,
    148 		y => c_pc_add_val,
    149 		z => s_adder_out
    150 	);
    151 
    152 	pc_map: pc port map (
    153 		clk => m_clk,
    154 		rst => m_rst,
    155 		ipc => s_adder_out,
    156 		opc => s_pc_out
    157 	);
    158 end struct;