mips_tb.vhd (778B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity mips_tb is 5 end mips_tb; 6 7 architecture behav of mips_tb is 8 9 signal s_m_clk: std_logic; 10 signal s_m_rst: std_logic; 11 12 component mips is port ( 13 m_clk: in std_logic; 14 m_rst: in std_logic 15 ); 16 end component; 17 18 begin 19 uut: mips port map ( 20 m_clk => s_m_clk, 21 m_rst => s_m_rst 22 ); 23 24 process begin 25 -- Reset everything. 26 s_m_rst <= '1'; 27 s_m_clk <= '0'; 28 wait for 250 ns; 29 30 s_m_clk <= '1'; 31 wait for 250 ns; 32 33 -- 1st cycle. 34 s_m_rst <= '0'; 35 s_m_clk <= '0'; 36 wait for 250 ns; 37 38 s_m_clk <= '1'; 39 wait for 250 ns; 40 41 -- 2nd cycle. 42 s_m_clk <= '0'; 43 wait for 250 ns; 44 45 s_m_clk <= '1'; 46 wait for 250 ns; 47 48 -- 3rd cycle. 49 s_m_clk <= '0'; 50 wait for 250 ns; 51 52 s_m_clk <= '1'; 53 wait for 250 ns; 54 end process; 55 end behav;