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pc.vhd (390B)


      1 library ieee;
      2 use ieee.std_logic_1164.all;
      3 
      4 entity pc is port (
      5 	clk:	in std_logic;
      6 	rst:	in std_logic;
      7 	ipc:	in std_logic_vector(31 downto 0);
      8 	opc:	out std_logic_vector(31 downto 0)
      9 );
     10 end pc;
     11 
     12 architecture behav of pc is
     13 begin
     14 	process (clk, rst) begin
     15 		if (rst = '1') then
     16 			opc <= x"00000000";
     17 		elsif (clk'event and clk = '0') then
     18 			opc <= ipc;
     19 		end if;
     20 	end process;
     21 end behav;