regfile_ext.vhd (1133B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.std_logic_unsigned.all; 4 use ieee.numeric_std.all; 5 6 entity regfile_ext is 7 generic ( 8 sz: natural := 32; 9 addrw: natural := 5 10 ); 11 port ( 12 idata: in std_logic_vector(sz-1 downto 0); 13 raddr1: in std_logic_vector(addrw-1 downto 0); 14 raddr2: in std_logic_vector(addrw-1 downto 0); 15 waddr: in std_logic_vector(addrw-1 downto 0); 16 we: in std_logic; 17 clk: in std_logic; 18 rst: in std_logic; 19 odata1: out std_logic_vector(sz-1 downto 0); 20 odata2: out std_logic_vector(sz-1 downto 0) 21 ); 22 end regfile_ext; 23 24 architecture behav of regfile_ext is 25 26 signal arrsz: natural := 32; 27 type regarr is array(0 to arrsz-1) of std_logic_vector(sz-1 downto 0); 28 -- Array used for initialization when rst = 1. 29 signal s_init: regarr := (others => x"ffffffff"); 30 signal regf: regarr; 31 32 begin 33 process (clk) begin 34 if (rst = '1') then 35 regf <= s_init; 36 elsif (clk'event and clk = '0') then 37 if (we = '1') then 38 regf(to_integer(unsigned(waddr))) <= idata; 39 end if; 40 end if; 41 end process; 42 odata1 <= regf(to_integer(unsigned(raddr1))); 43 odata2 <= regf(to_integer(unsigned(raddr2))); 44 end behav;