commit 21b3c13742df99aa940593fcbfd16394835cb8ff
parent ba95bb62eb498da7975174b7e1c55390363ace16
Author: Christos Margiolis <christos@margiolis.net>
Date: Sun, 14 May 2023 20:20:00 +0300
add verilog assignment
Diffstat:
8 files changed, 200 insertions(+), 0 deletions(-)
diff --git a/verilog_advanced_design/ex1/comp2.v b/verilog_advanced_design/ex1/comp2.v
@@ -0,0 +1,14 @@
+module comp2(a, y);
+ input [1:0] a;
+ output reg signed [3:0] y;
+
+ always @ (a) begin
+ if (a[0] > a[1])
+ y = 4'b0001;
+ else if (a[0] == a[1])
+ y = 4'b0000;
+ else
+ /* 2's complement */
+ y = 4'b1111;
+ end
+endmodule
diff --git a/verilog_advanced_design/ex1/comp2_tb.v b/verilog_advanced_design/ex1/comp2_tb.v
@@ -0,0 +1,21 @@
+module comp2_tb;
+ reg [1:0] tb_a;
+ wire signed [3:0] tb_y;
+
+ comp2 comp2_tb(
+ .a (tb_a),
+ .y (tb_y)
+ );
+
+ initial begin
+ $dumpfile("comp2.vcd");
+ $dumpvars(0, comp2_tb);
+
+ $monitor("time=%3d, tb_a=%b, tb_y=%d\n", $time, tb_a, tb_y);
+
+ tb_a <= 2'b01;
+ #20 tb_a <= 2'b00;
+ #20 tb_a <= 2'b10;
+ end
+endmodule
+
diff --git a/verilog_advanced_design/ex1/dff.v b/verilog_advanced_design/ex1/dff.v
@@ -0,0 +1,13 @@
+module dff(d, clk, rst, q);
+ input d;
+ input clk;
+ input rst;
+ output reg q;
+
+ always @ (posedge clk or posedge rst) begin
+ if (rst)
+ q = 0;
+ else
+ q = d;
+ end
+endmodule
diff --git a/verilog_advanced_design/ex1/dff_tb.v b/verilog_advanced_design/ex1/dff_tb.v
@@ -0,0 +1,31 @@
+module dff_tb;
+ reg tb_d;
+ reg tb_clk;
+ reg tb_rst;
+ wire q;
+
+ dff dff_tb(
+ .d (tb_d),
+ .clk (tb_clk),
+ .rst (tb_rst),
+ .q (tb_q)
+ );
+
+ always #20 tb_clk = ~tb_clk;
+
+ initial begin
+ $dumpfile("dff.vcd");
+ $dumpvars(0, dff_tb);
+
+ $monitor("time=%3d, tb_d=%b, tb_clk=%b, tb_rst=%b, tb_q=%b\n",
+ $time, tb_d, tb_clk, tb_rst, tb_q);
+
+ tb_clk <= 1;
+ tb_rst <= 0;
+ tb_d <= 1;
+ #40
+
+ tb_rst <= 1;
+ $finish;
+ end
+endmodule
diff --git a/verilog_advanced_design/ex1/mux4to1.v b/verilog_advanced_design/ex1/mux4to1.v
@@ -0,0 +1,16 @@
+module mux4to1 (a, s, y);
+ input [3:0] a;
+ input [1:0] s;
+ output reg y;
+
+ /* run whenever a or s change */
+ always @ (a, s) begin
+ case (s)
+ 2'b00: y = a[0];
+ 2'b01: y = a[1];
+ 2'b10: y = a[2];
+ 2'b11: y = a[3];
+ default: y = 0;
+ endcase
+ end
+endmodule
diff --git a/verilog_advanced_design/ex1/mux4to1_tb.v b/verilog_advanced_design/ex1/mux4to1_tb.v
@@ -0,0 +1,30 @@
+module mux4to1_tb;
+ reg [3:0] tb_a;
+ reg [1:0] tb_s;
+ wire tb_y;
+
+ mux4to1 mux4to1_tb (
+ .a (tb_a),
+ .s (tb_s),
+ .y (tb_y)
+ );
+
+ initial begin
+ /* used by gtkwave to display the testbench in waveforms */
+ $dumpfile("mux4to1.vcd");
+ $dumpvars(0, mux4to1_tb);
+
+ /* print the results to the command line */
+ $monitor("time=%3d, tb_a=%b, tb_s=%b, tb_y=%b\n",
+ $time, tb_a, tb_s, tb_y);
+
+ /* set a random 4bit value */
+ tb_a <= 4'b1101;
+
+ /* wait for 20 time units after each assignment */
+ tb_s <= 2'b00;
+ #20 tb_s <= 2'b01;
+ #20 tb_s <= 2'b10;
+ #20 tb_s <= 2'b11;
+ end
+endmodule
diff --git a/verilog_advanced_design/ex1/shift4.v b/verilog_advanced_design/ex1/shift4.v
@@ -0,0 +1,19 @@
+module shift4(d, clr, clk, shf, q);
+ input d;
+ input clr;
+ input clk;
+ input shf;
+ output reg [3:0] q;
+
+ /* run on a rising clock signal */
+ always @ (posedge clk) begin
+ if (clr)
+ q = 0;
+ else if (shf == 0)
+ q = (q << 1) | d;
+ else if (shf == 1)
+ q = (q >> 1) | d;
+ else
+ q = q;
+ end
+endmodule
diff --git a/verilog_advanced_design/ex1/shift4_tb.v b/verilog_advanced_design/ex1/shift4_tb.v
@@ -0,0 +1,56 @@
+module shift4_tb;
+ reg tb_d;
+ reg tb_clr;
+ reg tb_clk;
+ reg tb_shf;
+ wire [3:0] tb_q;
+
+ shift4 shift4_tb(
+ .d (tb_d),
+ .clr (tb_clr),
+ .clk (tb_clk),
+ .shf (tb_shf),
+ .q (tb_q)
+ );
+
+ /* switch clock values every 20 time units */
+ always #20 tb_clk = ~tb_clk;
+
+ initial begin
+ $dumpfile("shift4.vcd");
+ $dumpvars(0, shift4_tb);
+
+ $monitor("time=%3d, tb_d=%b, tb_clr=%b, tb_clk=%b, tb_shf=%b, tb_q=%b\n",
+ $time, tb_d, tb_clr, tb_clk, tb_shf, tb_q);
+
+ tb_clk <= 1; /* start clock */
+ tb_shf <= 0; /* shift to the left */
+ tb_d <= 1; /* data pin is 1 */
+
+ /* initialize q to 0 */
+ tb_clr <= 1;
+ #20 tb_clr <= 0;
+
+ /*
+ * q is currently 1, set the data pin to 0 so that we do not
+ * add 1 every time we shift
+ */
+ #20 tb_d <= 0;
+
+ /* shift 2 times to the left */
+ repeat (2) @ (posedge tb_clk)
+ ;
+
+ /* change shift direction */
+ #20 tb_shf <= 1;
+
+ /* shift 2 times to the right */
+ repeat (2) @ (posedge tb_clk)
+
+ /* clear q */
+ #20 tb_clr <= 1;
+ #20 tb_clr <= 0;
+
+ $finish;
+ end
+endmodule
