uni

commit 218f171f82ee07f7ef38dd8cf30ad1f4966f8d60
parent 21b3c13742df99aa940593fcbfd16394835cb8ff
Author: Christos Margiolis <christos@margiolis.net>
Date:   Sun, 14 May 2023 20:24:11 +0300

add semicolon

Diffstat:
M
verilog_advanced_design/ex1/shift4_tb.v
 | 
1
+

1 file changed, 1 insertion(+), 0 deletions(-)
diff --git a/verilog_advanced_design/ex1/shift4_tb.v b/verilog_advanced_design/ex1/shift4_tb.v
@@ -46,6 +46,7 @@ module shift4_tb;
 
 		/* shift 2 times to the right */
 		repeat (2) @ (posedge tb_clk)
+			;
 
 		/* clear q */
 		#20 tb_clr <= 1;