uni

commit 69a8a274c51e9ffac2d1258c83af00adc1910138
parent 218f171f82ee07f7ef38dd8cf30ad1f4966f8d60
Author: Christos Margiolis <christos@FreeBSD.org>
Date:   Sun,  4 Jun 2023 15:49:54 +0300

ex2

Diffstat:
A
verilog_advanced_design/ex2/alu.v
 | 
23
+++++++++++++++++++++++
A
verilog_advanced_design/ex2/alu_tb.v
 | 
52
++++++++++++++++++++++++++++++++++++++++++++++++++++
A
verilog_advanced_design/ex2/lfsr.v
 | 
12
++++++++++++
A
verilog_advanced_design/ex2/lfsr_tb.v
 | 
32
++++++++++++++++++++++++++++++++

4 files changed, 119 insertions(+), 0 deletions(-)
diff --git a/verilog_advanced_design/ex2/alu.v b/verilog_advanced_design/ex2/alu.v
@@ -0,0 +1,23 @@
+module alu(clk, in_a, in_b, alu_op, mux_sel, alu_out, mux_out);
+	input clk;
+	input [31:0] in_a;
+	input [31:0] in_b;
+	input [1:0] alu_op;
+	input mux_sel;
+	output reg [31:0] alu_out;
+	output reg [31:0] mux_out;
+
+	always @ (posedge clk) begin
+		case (alu_op)
+			2'b00: alu_out = in_a & in_b;
+			2'b01: alu_out = in_a | in_b;
+			2'b10: alu_out = in_a + in_b;
+			2'b11: alu_out = in_a - in_b;
+			default: alu_out = 0;
+		endcase
+		if (mux_sel == 0)
+			mux_out = alu_out;
+		else
+			mux_out = in_b;
+	end
+endmodule
diff --git a/verilog_advanced_design/ex2/alu_tb.v b/verilog_advanced_design/ex2/alu_tb.v
@@ -0,0 +1,52 @@
+module alu_tb;
+	reg tb_clk;
+	reg [31:0] tb_in_a;
+	reg [31:0] tb_in_b;
+	reg [1:0] tb_alu_op;
+	reg tb_mux_sel;
+	wire [31:0] tb_alu_out;
+	wire [31:0] tb_mux_out;
+
+	alu alu_tb(
+		.clk (tb_clk),
+		.in_a (tb_in_a),
+		.in_b (tb_in_b),
+		.alu_op (tb_alu_op),
+		.mux_sel (tb_mux_sel),
+		.alu_out (tb_alu_out),
+		.mux_out (tb_mux_out)
+	);
+
+	always #20 tb_clk = ~tb_clk;
+
+	initial begin
+		$dumpfile("alu.vcd");
+		$dumpvars(0, alu_tb);
+
+		$monitor("time=%3d, clk=%b, in_a=%b, in_b=%b, alu_op=%b, mux_sel=%b, alu_out=%b, mux_out=%b\n",
+		    $time, tb_clk, tb_in_a, tb_in_b, tb_alu_op, tb_mux_sel,
+		    tb_alu_out, tb_mux_out);
+
+		tb_clk <= 0;
+	
+		tb_in_a <= 16'hffff;
+		tb_in_b <= 16'hc23a;
+		tb_alu_op <= 2'b01;
+		tb_mux_sel <= 0;
+		#40
+
+		tb_in_a <= 16'hab12;
+		tb_in_b <= 16'h12ba;
+		tb_alu_op <= 2'b10;
+		tb_mux_sel <= 0;
+		#40
+
+		tb_in_a <= 16'h12c5;
+		tb_in_b <= 16'hd145;
+		tb_alu_op <= 2'b11;
+		tb_mux_sel <= 1;
+		#40
+
+		$finish;
+	end
+endmodule
diff --git a/verilog_advanced_design/ex2/lfsr.v b/verilog_advanced_design/ex2/lfsr.v
@@ -0,0 +1,12 @@
+module lfsr(clk, rst, out);
+	input clk;
+	input rst;
+	output reg [2:0] out;
+
+	always @ (posedge clk) begin
+		if (rst)
+			out = 4'b101;
+		else
+			out = {out[1:0],(out[2] ^ out[1])};
+	end
+endmodule
diff --git a/verilog_advanced_design/ex2/lfsr_tb.v b/verilog_advanced_design/ex2/lfsr_tb.v
@@ -0,0 +1,32 @@
+module lfsr_tb;
+	reg tb_clk;
+	reg tb_rst;
+	wire [2:0] tb_out;
+
+	lfsr lfsr_tb(
+		.clk (tb_clk),
+		.rst (tb_rst),
+		.out (tb_out)
+	);
+
+	always #20 tb_clk = ~tb_clk;
+
+	initial begin
+		$dumpfile("lfsr.vcd");
+		$dumpvars(0, lfsr_tb);
+
+		$monitor("time=%3d, clk=%b, rst=%b, out=%b\n",
+		    $time, tb_clk, tb_rst, tb_out);
+
+		tb_clk <= 0;
+		tb_rst <= 1;
+		#20
+
+		tb_rst <= 0;
+
+		repeat (4) @ (posedge tb_clk)
+			;
+
+		$finish;
+	end
+endmodule