commit ae6a0818a233734bb79a28ff653695f629c58828 parent 309d7ea994ccc1197093dcb4da1eafccf1af4ac1 Author: Christos Margiolis <christos@margiolis.net> Date: Tue, 6 Jul 2021 16:07:29 +0300 started vhdl project Diffstat:
18 files changed, 218 insertions(+), 23 deletions(-)
diff --git a/README b/README @@ -1,3 +1,4 @@ uni === + My university programming assignments. diff --git a/cpp_oop/game/Engine.cc b/cpp_oop/game/Engine.cc @@ -14,22 +14,21 @@ enum Color { Engine::Engine(const char *mapfile, const char *scorefile, const char *name) { /* - * Initialize curses(3) first so we can get the terminal's dimensions - * and use them in `load_map`. - */ - if (!init_curses()) - throw std::runtime_error("init_curses failed"); - - /* * We'll use std::runtime_error exceptions here because we - * want to display a useful error message since `load_map` - * and `Score`'s constructor have many points of failure. + * want to display a useful error message since there are + * many points of failure. * If we do catch an exception, we'll just "forward" it * to `main`. */ try { + /* + * Initialize curses(3) first so we can get the terminal's + * dimensions and use them in `load_map`. + */ + init_curses(); load_map(mapfile); score = new Score(scorefile, name); + init_gamewin(); } catch (const std::ios_base::failure& e) { /* * Kill the curses window, otherwise the terminal output @@ -41,10 +40,6 @@ Engine::Engine(const char *mapfile, const char *scorefile, const char *name) (void)endwin(); throw std::runtime_error("error: " + std::string(e.what())); } - if (!init_gamewin()) { - (void)endwin(); - throw std::runtime_error("init_gamewin failed"); - } reset_entities(); init_popup_msgs(); @@ -94,13 +89,13 @@ Engine::reset_entities() /* * Initialize curses(3) environment */ -bool +void Engine::init_curses() { std::vector<int> colors; if (!initscr()) - return false; + throw std::runtime_error("init_curses failed"); /* Don't echo keypresses. */ noecho(); /* Disable line buffering. */ @@ -139,15 +134,13 @@ Engine::init_curses() use_default_colors(); for (int i = 1; i < Color::LAST; i++) (void)init_pair(i, colors[i-1], -1); - - return true; } /* * Initiliaze the game window. Having a seperate window for the game * will make it easier to handle the map and player input. */ -bool +void Engine::init_gamewin() { int wr, wc, wy, wx; @@ -157,11 +150,9 @@ Engine::init_gamewin() wy = CENTER(ymax, wr); wx = CENTER(xmax, wc); if ((gw = newwin(wr, wc, wy, wx)) == NULL) - return false; + throw std::runtime_error("init_gamewin failed"); box(gw, 0, 0); (void)getmaxyx(gw, wymax, wxmax); - - return true; } void diff --git a/cpp_oop/game/Engine.hpp b/cpp_oop/game/Engine.hpp @@ -73,8 +73,8 @@ public: private: void free_entities(); void reset_entities(); - bool init_curses(); - bool init_gamewin(); + void init_curses(); + void init_gamewin(); void load_map(const char *mapfile); void calc_pos(int *x, int *y); void init_entities(); diff --git a/vhdl_digital_design/project/part0/Makefile b/vhdl_digital_design/project/part0/Makefile @@ -0,0 +1 @@ +include ../../Makefile diff --git a/vhdl_digital_design/project/part0/dec2to4.vhd b/vhdl_digital_design/project/part0/dec2to4.vhd @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dec2to4 is port ( + a: in std_logic_vector(1 downto 0); + d: out std_logic_vector(3 downto 0) +); +end dec2to4; + +architecture dataflow of dec2to4 is +begin + d(0) <= not a(0) and not a(1); + d(1) <= not a(0) and a(1); + d(2) <= a(0) and not a(1); + d(3) <= a(0) and a(1); +end dataflow; diff --git a/vhdl_digital_design/project/part0/mux2to1.vhd b/vhdl_digital_design/project/part0/mux2to1.vhd @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity mux2to1 is port ( + a: in std_logic; + b: in std_logic; + s: in std_logic; + d: out std_logic +); +end mux2to1; + +architecture dataflow of mux2to1 is +begin + d <= a when s = '1' else b; +end dataflow; diff --git a/vhdl_digital_design/project/part0/mux2to1gen.vhd b/vhdl_digital_design/project/part0/mux2to1gen.vhd @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity mux2to1gen is +generic ( + dw: natural := 4 +); +port ( + a: in std_logic_vector(dw-1 downto 0); + b: in std_logic_vector(dw-1 downto 0); + s: in std_logic; + c: out std_logic_vector(dw-1 downto 0) +); +end mux2to1gen; + +architecture dataflow of mux2to1gen is +begin + c <= a when s = '1' else b; +end dataflow; diff --git a/vhdl_digital_design/project/part0/mux2to1gen_tb.png b/vhdl_digital_design/project/part0/mux2to1gen_tb.png Binary files differ. diff --git a/vhdl_digital_design/project/part0/mux2to1gen_tb.vhd b/vhdl_digital_design/project/part0/mux2to1gen_tb.vhd @@ -0,0 +1,46 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity mux2to1gen_tb is +end mux2to1gen_tb; + +architecture behav of mux2to1gen_tb is + +signal s_dw: natural := 4; +signal s_a: std_logic_vector(s_dw-1 downto 0); +signal s_b: std_logic_vector(s_dw-1 downto 0); +signal s_s: std_logic; +signal s_c: std_logic_vector(s_dw-1 downto 0); + +component mux2to1gen is +generic ( + dw: natural := 4 +); +port ( + a: in std_logic_vector(dw-1 downto 0); + b: in std_logic_vector(dw-1 downto 0); + s: in std_logic; + c: out std_logic_vector(dw-1 downto 0) +); +end component; + +begin + uut: mux2to1gen port map ( + a => s_a, + b => s_b, + s => s_s, + c => s_c + ); + + process begin + s_a <= "0000"; + s_b <= "1101"; + s_s <= '0'; + wait for 250 ns; + + s_a <= "0000"; + s_b <= "1101"; + s_s <= '1'; + wait for 250 ns; + end process; +end behav; diff --git a/vhdl_digital_design/project/part1/Makefile b/vhdl_digital_design/project/part1/Makefile @@ -0,0 +1 @@ +include ../../Makefile diff --git a/vhdl_digital_design/project/part1/alu.vhd b/vhdl_digital_design/project/part1/alu.vhd @@ -0,0 +1,35 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity alu is +generic ( + dw: natural := 4 +); +port ( + alu_in1: in std_logic_vector(dw-1 downto 0); + alu_in2: in std_logic_vector(dw-1 downto 0); + alu_ctrl: in std_logic_vector(3 downto 0); + alu_out: out std_logic_vector(dw-1 downto 0); + alu_zero: out std_logic +); +end alu; + +architecture behav of alu is +signal sig: std_logic_vector(dw-1 downto 0); + +begin + process (alu_ctrl) begin + case alu_ctrl is + when "0000" => sig <= alu_in1 and alu_in2; + when "0001" => sig <= alu_in1 or alu_in2; + when "0010" => + sig <= std_logic_vector(signed(alu_in1) + signed(alu_in2)); + when "0110" => + sig <= std_logic_vector(signed(alu_in1) - signed(alu_in2)); + when others => sig <= (others => 'X'); + end case; + end process; + alu_zero <= '1' when sig = "0000" else '0'; + alu_out <= sig; +end behav; diff --git a/vhdl_digital_design/project/part1/alu_tb.png b/vhdl_digital_design/project/part1/alu_tb.png Binary files differ. diff --git a/vhdl_digital_design/project/part1/alu_tb.vhd b/vhdl_digital_design/project/part1/alu_tb.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity alu_tb is +end alu_tb; + +architecture behav of alu_tb is + +signal s_dw: natural := 4; +signal s_alu_in1: std_logic_vector(s_dw-1 downto 0); +signal s_alu_in2: std_logic_vector(s_dw-1 downto 0); +signal s_alu_ctrl: std_logic_vector(3 downto 0); +signal s_alu_out: std_logic_vector(s_dw-1 downto 0); +signal s_alu_zero: std_logic; + +component alu is +generic ( + dw: natural := 4 +); +port ( + alu_in1: in std_logic_vector(dw-1 downto 0); + alu_in2: in std_logic_vector(dw-1 downto 0); + alu_ctrl: in std_logic_vector(3 downto 0); + alu_out: out std_logic_vector(dw-1 downto 0); + alu_zero: out std_logic +); +end component; + +begin + uut: alu port map ( + alu_in1 => s_alu_in1, + alu_in2 => s_alu_in2, + alu_ctrl => s_alu_ctrl, + alu_out => s_alu_out, + alu_zero => s_alu_zero + ); + + process begin + s_alu_in1 <= "0010"; + s_alu_in2 <= "0100"; + s_alu_ctrl <= "0010"; + wait for 250 ns; + + s_alu_in1 <= "0100"; + s_alu_in2 <= "1111"; + s_alu_ctrl <= "0000"; + wait for 250 ns; + + s_alu_in1 <= "0100"; + s_alu_in2 <= "1111"; + s_alu_ctrl <= "0001"; + wait for 250 ns; + + s_alu_in1 <= "0100"; + s_alu_in2 <= "0010"; + s_alu_ctrl <= "0110"; + wait for 250 ns; + + s_alu_in1 <= "0100"; + s_alu_in2 <= "0110"; + s_alu_ctrl <= "0110"; + wait for 250 ns; + end process; +end behav; diff --git a/vhdl_digital_design/project/part2/Makefile b/vhdl_digital_design/project/part2/Makefile @@ -0,0 +1 @@ +include ../../Makefile diff --git a/vhdl_digital_design/project/part3/Makefile b/vhdl_digital_design/project/part3/Makefile @@ -0,0 +1 @@ +include ../../Makefile diff --git a/vhdl_digital_design/project/part4/Makefile b/vhdl_digital_design/project/part4/Makefile @@ -0,0 +1 @@ +include ../../Makefile diff --git a/vhdl_digital_design/project/part5/Makefile b/vhdl_digital_design/project/part5/Makefile @@ -0,0 +1 @@ +include ../../Makefile diff --git a/vhdl_digital_design/project/part6/Makefile b/vhdl_digital_design/project/part6/Makefile @@ -0,0 +1 @@ +include ../../Makefile
