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commit 11aa99766552691933815eba3a31755e933528f9
parent 26f662f912abd691fbf6e844a9bac6125d7528a0
Author: Christos Margiolis <christos@margiolis.net>
Date:   Fri, 16 Jul 2021 15:48:46 +0300

mips isn't finished yet

Diffstat:
Mvhdl_digital_design/project/part5_regfile/regfile_ext.vhd | 2+-
Avhdl_digital_design/project/part6_mips_r_ops/adder32.vhd | 11+++++++++++
Avhdl_digital_design/project/part6_mips_r_ops/alu.vhd | 35+++++++++++++++++++++++++++++++++++
Avhdl_digital_design/project/part6_mips_r_ops/alu_ctrl.vhd | 19+++++++++++++++++++
Avhdl_digital_design/project/part6_mips_r_ops/ctrl.vhd | 30++++++++++++++++++++++++++++++
Avhdl_digital_design/project/part6_mips_r_ops/instrmem.vhd | 36++++++++++++++++++++++++++++++++++++
Avhdl_digital_design/project/part6_mips_r_ops/mips.vhd | 76++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Avhdl_digital_design/project/part6_mips_r_ops/pc.vhd | 10++++++++++
Avhdl_digital_design/project/part6_mips_r_ops/regfile_ext.vhd | 44++++++++++++++++++++++++++++++++++++++++++++
9 files changed, 262 insertions(+), 1 deletion(-)

diff --git a/vhdl_digital_design/project/part5_regfile/regfile_ext.vhd b/vhdl_digital_design/project/part5_regfile/regfile_ext.vhd @@ -25,7 +25,7 @@ architecture behav of regfile_ext is signal arrsz: natural := 8; type regarr is array(0 to arrsz-1) of std_logic_vector(sz-1 downto 0); --- Empty register array used for initialized when rst = 1. +-- Empty register array used for initialization when rst = 1. signal s_init: regarr := (others => (others => '0')); signal regf: regarr; diff --git a/vhdl_digital_design/project/part6_mips_r_ops/adder32.vhd b/vhdl_digital_design/project/part6_mips_r_ops/adder32.vhd @@ -0,0 +1,11 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity adder32 is port ( +); +end adder32; + +architecture behav of adder32 is + +begin +end behav; diff --git a/vhdl_digital_design/project/part6_mips_r_ops/alu.vhd b/vhdl_digital_design/project/part6_mips_r_ops/alu.vhd @@ -0,0 +1,35 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity alu is +generic ( + sz: natural := 32 +); +port ( + alu_in1: in std_logic_vector(sz-1 downto 0); + alu_in2: in std_logic_vector(sz-1 downto 0); + alu_ctrl: in std_logic_vector(3 downto 0); + alu_out: out std_logic_vector(sz-1 downto 0); + alu_zero: out std_logic +); +end alu; + +architecture behav of alu is +signal sig: std_logic_vector(sz-1 downto 0); + +begin + process (alu_ctrl) begin + case alu_ctrl is + when "0000" => sig <= alu_in1 and alu_in2; + when "0001" => sig <= alu_in1 or alu_in2; + when "0010" => + sig <= std_logic_vector(signed(alu_in1) + signed(alu_in2)); + when "0110" => + sig <= std_logic_vector(signed(alu_in1) - signed(alu_in2)); + when others => sig <= (others => 'X'); + end case; + end process; + alu_zero <= '1' when sig = x"00000000" else '0'; + alu_out <= sig; +end behav; diff --git a/vhdl_digital_design/project/part6_mips_r_ops/alu_ctrl.vhd b/vhdl_digital_design/project/part6_mips_r_ops/alu_ctrl.vhd @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity alu_ctrl is port ( + funct: in std_logic_vector(5 downto 0); + alu_op: in std_logic_vector(1 downto 0); + op: out std_logic_vector(3 downto 0) +); +end alu_ctrl; + +architecture dataflow of alu_ctrl is +begin + op <= "0010" when (alu_op = "00" or (alu_op = "10" and funct = "100000")) else + "0110" when (alu_op = "01" or (alu_op = "10" and funct = "100010")) else + "0000" when (alu_op = "10" and funct = "100100") else + "0001" when (alu_op = "10" and funct = "100101") else + "0111" when (alu_op = "10" and funct = "101010") else + "1111"; +end dataflow; diff --git a/vhdl_digital_design/project/part6_mips_r_ops/ctrl.vhd b/vhdl_digital_design/project/part6_mips_r_ops/ctrl.vhd @@ -0,0 +1,30 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ctrl is port ( + funct: in std_logic_vector(5 downto 0); + reg_dst: out std_logic; + reg_wr: out std_logic; + alu_src: out std_logic; + branch: out std_logic; + mem_rd: out std_logic; + mem_wr: out std_logic; + mem_toreg: out std_logic; + alu_op: out std_logic_vector(1 downto 0) +); +end ctrl; + +architecture dataflow of ctrl is +begin + reg_dst <= '1' when funct = "000000" else '0'; + reg_wr <= '1' when funct = "000000" or funct = "100011" else '0'; + alu_src <= '1' when funct = "100011" or funct = "101011" else '0'; + branch <= '1' when funct = "000100" else '0'; + mem_rd <= '1' when funct = "100011" else '0'; + mem_wr <= '1' when funct = "101011" else '0'; + mem_toreg <= '1' when funct = "100011" else '0'; + with funct select + alu_op <= "10" when "000000", + "01" when "000100", + "00" when others; +end dataflow; diff --git a/vhdl_digital_design/project/part6_mips_r_ops/instrmem.vhd b/vhdl_digital_design/project/part6_mips_r_ops/instrmem.vhd @@ -0,0 +1,36 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity instrmem is port ( + addr: in std_logic_vector(3 downto 0); + c: out std_logic_vector(31 downto 0) +); +end instrmem; + +architecture dataflow of instrmem is + +type instr_arr is array(0 to 15) of std_logic_vector (31 downto 0); +constant instr_mem: instr_arr := ( + "00000000000000000000000000000000", -- 0 + "00000000000000000000000000000000", -- 1 + "00000000000000000000000000000000", -- 2 + "00000000000000000000000000000000", -- 3 + "00000000000000000000000000000000", -- 4 + "00000000000000000000000000000000", -- 5 + "00000000000000000000000000000000", -- 6 + "00000000000000000000000000000000", -- 7 + "00000000000000000000000000000000", -- 8 + "00000000000000000000000000000000", -- 9 + "00000000000000000000000000000000", -- 10 + "00000000000000000000000000000000", -- 11 + "00000000000000000000000000000000", -- 12 + "00000000000000000000000000000000", -- 13 + "00000000000000000000000000000000", -- 14 + "00000000000000000000000000000000" -- 15 +); + +begin + c <= instr_mem(to_integer(unsigned(addr))); +end dataflow; diff --git a/vhdl_digital_design/project/part6_mips_r_ops/mips.vhd b/vhdl_digital_design/project/part6_mips_r_ops/mips.vhd @@ -0,0 +1,76 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity mips is port ( +); +end mips; + +architecture struct of mips is + +component alu is +generic ( + sz: natural := 32 +); +port ( + alu_in1: in std_logic_vector(sz-1 downto 0); + alu_in2: in std_logic_vector(sz-1 downto 0); + alu_ctrl: in std_logic_vector(3 downto 0); + alu_out: out std_logic_vector(sz-1 downto 0); + alu_zero: out std_logic +); +end component; + +component regfile_ext is +generic ( + sz: natural := 32; + addrw: natural := 5 +); +port ( + idata: in std_logic_vector(sz-1 downto 0); + raddr1: in std_logic_vector(addrw-1 downto 0); + raddr2: in std_logic_vector(addrw-1 downto 0); + waddr: in std_logic_vector(addrw-1 downto 0); + we: in std_logic; + clk: in std_logic; + rst: in std_logic; + odata1: out std_logic_vector(sz-1 downto 0); + odata2: out std_logic_vector(sz-1 downto 0) +); +end component; + +component instrmem is port ( + addr: in std_logic_vector(3 downto 0); + c: out std_logic_vector(31 downto 0) +); +end component; + +component ctrl is port ( + funct: in std_logic_vector(5 downto 0); + reg_dst: out std_logic; + reg_wr: out std_logic; + alu_src: out std_logic; + branch: out std_logic; + mem_rd: out std_logic; + mem_wr: out std_logic; + mem_toreg: out std_logic; + alu_op: out std_logic_vector(1 downto 0) +); +end component; + +component alu_ctrl is port ( + funct: in std_logic_vector(5 downto 0); + alu_op: in std_logic_vector(1 downto 0); + op: out std_logic_vector(3 downto 0) +); +end component; + +component pc is port ( +); +end component; + +component adder32 is port ( +); +end component; + +begin +end struct; diff --git a/vhdl_digital_design/project/part6_mips_r_ops/pc.vhd b/vhdl_digital_design/project/part6_mips_r_ops/pc.vhd @@ -0,0 +1,10 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity pc is port ( +); +end pc; + +architecture behav of pc is +begin +end behav; diff --git a/vhdl_digital_design/project/part6_mips_r_ops/regfile_ext.vhd b/vhdl_digital_design/project/part6_mips_r_ops/regfile_ext.vhd @@ -0,0 +1,44 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity regfile_ext is +generic ( + sz: natural := 32; + addrw: natural := 5 +); +port ( + idata: in std_logic_vector(sz-1 downto 0); + raddr1: in std_logic_vector(addrw-1 downto 0); + raddr2: in std_logic_vector(addrw-1 downto 0); + waddr: in std_logic_vector(addrw-1 downto 0); + we: in std_logic; + clk: in std_logic; + rst: in std_logic; + odata1: out std_logic_vector(sz-1 downto 0); + odata2: out std_logic_vector(sz-1 downto 0) +); +end regfile_ext; + +architecture behav of regfile_ext is + +signal arrsz: natural := 32; +type regarr is array(0 to arrsz-1) of std_logic_vector(sz-1 downto 0); +-- Array used for initialization when rst = 1. +signal s_init: regarr := (others => x"ffffffff"); +signal regf: regarr; + +begin + process (clk) begin + if (rst = '1') then + regf <= s_init; + elsif (clk'event and clk = '0') then + if (we = '1') then + regf(to_integer(unsigned(waddr))) <= idata; + end if; + end if; + end process; + odata1 <= regf(to_integer(unsigned(raddr1))); + odata2 <= regf(to_integer(unsigned(raddr2))); +end behav;