commit 26f662f912abd691fbf6e844a9bac6125d7528a0 parent 52ce0098f86ac38367b6c68ca71ae49243ae4b6f Author: Christos Margiolis <christos@margiolis.net> Date: Thu, 15 Jul 2021 17:15:00 +0300 part5 done Diffstat:
13 files changed, 395 insertions(+), 46 deletions(-)
diff --git a/vhdl_digital_design/project/part0_mux_dec/mux2to1gen.vhd b/vhdl_digital_design/project/part0_mux_dec/mux2to1gen.vhd @@ -3,13 +3,13 @@ use ieee.std_logic_1164.all; entity mux2to1gen is generic ( - dw: natural := 4 + sz: natural := 4 ); port ( - a: in std_logic_vector(dw-1 downto 0); - b: in std_logic_vector(dw-1 downto 0); + a: in std_logic_vector(sz-1 downto 0); + b: in std_logic_vector(sz-1 downto 0); s: in std_logic; - c: out std_logic_vector(dw-1 downto 0) + c: out std_logic_vector(sz-1 downto 0) ); end mux2to1gen; diff --git a/vhdl_digital_design/project/part0_mux_dec/mux2to1gen_tb.vhd b/vhdl_digital_design/project/part0_mux_dec/mux2to1gen_tb.vhd @@ -6,21 +6,21 @@ end mux2to1gen_tb; architecture behav of mux2to1gen_tb is -signal s_dw: natural := 4; -signal s_a: std_logic_vector(s_dw-1 downto 0); -signal s_b: std_logic_vector(s_dw-1 downto 0); +signal s_sz: natural := 4; +signal s_a: std_logic_vector(s_sz-1 downto 0); +signal s_b: std_logic_vector(s_sz-1 downto 0); signal s_s: std_logic; -signal s_c: std_logic_vector(s_dw-1 downto 0); +signal s_c: std_logic_vector(s_sz-1 downto 0); component mux2to1gen is generic ( - dw: natural := 4 + sz: natural := 4 ); port ( - a: in std_logic_vector(dw-1 downto 0); - b: in std_logic_vector(dw-1 downto 0); + a: in std_logic_vector(sz-1 downto 0); + b: in std_logic_vector(sz-1 downto 0); s: in std_logic; - c: out std_logic_vector(dw-1 downto 0) + c: out std_logic_vector(sz-1 downto 0) ); end component; diff --git a/vhdl_digital_design/project/part1_alu/alu.vhd b/vhdl_digital_design/project/part1_alu/alu.vhd @@ -4,19 +4,19 @@ use ieee.numeric_std.all; entity alu is generic ( - dw: natural := 4 + sz: natural := 4 ); port ( - alu_in1: in std_logic_vector(dw-1 downto 0); - alu_in2: in std_logic_vector(dw-1 downto 0); + alu_in1: in std_logic_vector(sz-1 downto 0); + alu_in2: in std_logic_vector(sz-1 downto 0); alu_ctrl: in std_logic_vector(3 downto 0); - alu_out: out std_logic_vector(dw-1 downto 0); + alu_out: out std_logic_vector(sz-1 downto 0); alu_zero: out std_logic ); end alu; architecture behav of alu is -signal sig: std_logic_vector(dw-1 downto 0); +signal sig: std_logic_vector(sz-1 downto 0); begin process (alu_ctrl) begin diff --git a/vhdl_digital_design/project/part1_alu/alu_tb.vhd b/vhdl_digital_design/project/part1_alu/alu_tb.vhd @@ -7,22 +7,22 @@ end alu_tb; architecture behav of alu_tb is -signal s_dw: natural := 4; -signal s_alu_in1: std_logic_vector(s_dw-1 downto 0); -signal s_alu_in2: std_logic_vector(s_dw-1 downto 0); +signal s_sz: natural := 4; +signal s_alu_in1: std_logic_vector(s_sz-1 downto 0); +signal s_alu_in2: std_logic_vector(s_sz-1 downto 0); signal s_alu_ctrl: std_logic_vector(3 downto 0); -signal s_alu_out: std_logic_vector(s_dw-1 downto 0); +signal s_alu_out: std_logic_vector(s_sz-1 downto 0); signal s_alu_zero: std_logic; component alu is generic ( - dw: natural := 4 + sz: natural := 4 ); port ( - alu_in1: in std_logic_vector(dw-1 downto 0); - alu_in2: in std_logic_vector(dw-1 downto 0); + alu_in1: in std_logic_vector(sz-1 downto 0); + alu_in2: in std_logic_vector(sz-1 downto 0); alu_ctrl: in std_logic_vector(3 downto 0); - alu_out: out std_logic_vector(dw-1 downto 0); + alu_out: out std_logic_vector(sz-1 downto 0); alu_zero: out std_logic ); end component; diff --git a/vhdl_digital_design/project/part2_alu_ctrl/alu.vhd b/vhdl_digital_design/project/part2_alu_ctrl/alu.vhd @@ -4,19 +4,19 @@ use ieee.numeric_std.all; entity alu is generic ( - dw: natural := 4 + sz: natural := 4 ); port ( - alu_in1: in std_logic_vector(dw-1 downto 0); - alu_in2: in std_logic_vector(dw-1 downto 0); + alu_in1: in std_logic_vector(sz-1 downto 0); + alu_in2: in std_logic_vector(sz-1 downto 0); alu_ctrl: in std_logic_vector(3 downto 0); - alu_out: out std_logic_vector(dw-1 downto 0); + alu_out: out std_logic_vector(sz-1 downto 0); alu_zero: out std_logic ); end alu; architecture behav of alu is -signal sig: std_logic_vector(dw-1 downto 0); +signal sig: std_logic_vector(sz-1 downto 0); begin process (alu_ctrl) begin diff --git a/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl_test_alu.vhd b/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl_test_alu.vhd @@ -2,14 +2,14 @@ library ieee; use ieee.std_logic_1164.all; entity alu_ctrl_test_alu is generic ( - t_dw: natural := 4 + t_sz: natural := 4 ); port ( t_funct: in std_logic_vector(5 downto 0); t_alu_op: in std_logic_vector(1 downto 0); - t_alu_in1: in std_logic_vector(t_dw-1 downto 0); - t_alu_in2: in std_logic_vector(t_dw-1 downto 0); - t_alu_out: out std_logic_vector(t_dw-1 downto 0); + t_alu_in1: in std_logic_vector(t_sz-1 downto 0); + t_alu_in2: in std_logic_vector(t_sz-1 downto 0); + t_alu_out: out std_logic_vector(t_sz-1 downto 0); t_alu_zero: out std_logic ); end alu_ctrl_test_alu; @@ -26,13 +26,13 @@ component alu_ctrl is port ( end component; component alu is generic ( - dw: natural := 4 + sz: natural := 4 ); port ( - alu_in1: in std_logic_vector(dw-1 downto 0); - alu_in2: in std_logic_vector(dw-1 downto 0); + alu_in1: in std_logic_vector(sz-1 downto 0); + alu_in2: in std_logic_vector(sz-1 downto 0); alu_ctrl: in std_logic_vector(3 downto 0); - alu_out: out std_logic_vector(dw-1 downto 0); + alu_out: out std_logic_vector(sz-1 downto 0); alu_zero: out std_logic ); end component; diff --git a/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl_test_alu_tb.vhd b/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl_test_alu_tb.vhd @@ -6,23 +6,23 @@ end alu_ctrl_test_alu_tb; architecture behav of alu_ctrl_test_alu_tb is -signal s_dw: natural := 4; +signal s_sz: natural := 4; signal s_t_funct: std_logic_vector(5 downto 0); signal s_t_alu_op: std_logic_vector(1 downto 0); -signal s_t_alu_in1: std_logic_vector(s_dw-1 downto 0); -signal s_t_alu_in2: std_logic_vector(s_dw-1 downto 0); -signal s_t_alu_out: std_logic_vector(s_dw-1 downto 0); +signal s_t_alu_in1: std_logic_vector(s_sz-1 downto 0); +signal s_t_alu_in2: std_logic_vector(s_sz-1 downto 0); +signal s_t_alu_out: std_logic_vector(s_sz-1 downto 0); signal s_t_alu_zero: std_logic; component alu_ctrl_test_alu is generic ( - t_dw: natural := 4 + t_sz: natural := 4 ); port ( t_funct: in std_logic_vector(5 downto 0); t_alu_op: in std_logic_vector(1 downto 0); - t_alu_in1: in std_logic_vector(t_dw-1 downto 0); - t_alu_in2: in std_logic_vector(t_dw-1 downto 0); - t_alu_out: out std_logic_vector(t_dw-1 downto 0); + t_alu_in1: in std_logic_vector(t_sz-1 downto 0); + t_alu_in2: in std_logic_vector(t_sz-1 downto 0); + t_alu_out: out std_logic_vector(t_sz-1 downto 0); t_alu_zero: out std_logic ); end component; diff --git a/vhdl_digital_design/project/part5_regfile/reg.vhd b/vhdl_digital_design/project/part5_regfile/reg.vhd @@ -0,0 +1,29 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity reg is +generic ( + sz: natural := 4 +); +port ( + d: in std_logic_vector(sz-1 downto 0); + rst: in std_logic; + clk: in std_logic; + q: out std_logic_vector(sz-1 downto 0) +); +end reg; + +architecture behav of reg is + +-- We want to automatically initialize the vector no matter its size. +signal s_init: std_logic_vector(sz-1 downto 0) := (others => '0'); + +begin + process (rst, clk) begin + if (rst = '0') then + q <= s_init; + elsif (rising_edge(clk)) then + q <= d; + end if; + end process; +end behav; diff --git a/vhdl_digital_design/project/part5_regfile/reg_tb.vhd b/vhdl_digital_design/project/part5_regfile/reg_tb.vhd @@ -0,0 +1,59 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity reg_tb is +end reg_tb; + +architecture behav of reg_tb is + +signal s_sz: natural := 4; +signal s_d: std_logic_vector(s_sz-1 downto 0); +signal s_rst: std_logic; +signal s_clk: std_logic; +signal s_q: std_logic_vector(s_sz-1 downto 0); + +component reg is +generic ( + sz: natural := 4 +); +port ( + d: in std_logic_vector(sz-1 downto 0); + rst: in std_logic; + clk: in std_logic; + q: out std_logic_vector(sz-1 downto 0) +); +end component; + +begin + uut: reg port map ( + d => s_d, + rst => s_rst, + clk => s_clk, + q => s_q + ); + + process begin + s_rst <= '1'; + s_clk <= '0'; + s_d <= "0010"; + wait for 250 ns; + + s_clk <= '1'; + wait for 250 ns; + + s_clk <= '0'; + s_d <= "1110"; + wait for 250 ns; + + s_clk <= '1'; + wait for 250 ns; + + s_clk <= '0'; + s_d <= "1010"; + wait for 250 ns; + + s_rst <= '0'; + s_clk <= '1'; + wait for 250 ns; + end process; +end behav; diff --git a/vhdl_digital_design/project/part5_regfile/regfile.vhd b/vhdl_digital_design/project/part5_regfile/regfile.vhd @@ -0,0 +1,35 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity regfile is +generic ( + sz: natural := 4; + addrw: natural := 3 +); +port ( + idata: in std_logic_vector(sz-1 downto 0); + addr: in std_logic_vector(addrw-1 downto 0); + we: in std_logic; + clk: in std_logic; + odata: out std_logic_vector(sz-1 downto 0) +); +end regfile; + +architecture behav of regfile is + +signal arrsz: natural := 4; +type regarr is array(arrsz-1 downto 0) of std_logic_vector(sz-1 downto 0); +signal regf: regarr; + +begin + process (clk) begin + if (clk'event and clk = '0') then + if (we = '1') then + regf(to_integer(unsigned(addr))) <= idata; + end if; + end if; + end process; + odata <= regf(to_integer(unsigned(addr))); +end behav; diff --git a/vhdl_digital_design/project/part5_regfile/regfile_ext.vhd b/vhdl_digital_design/project/part5_regfile/regfile_ext.vhd @@ -0,0 +1,44 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity regfile_ext is +generic ( + sz: natural := 4; + addrw: natural := 3 +); +port ( + idata: in std_logic_vector(sz-1 downto 0); + raddr1: in std_logic_vector(addrw-1 downto 0); + raddr2: in std_logic_vector(addrw-1 downto 0); + waddr: in std_logic_vector(addrw-1 downto 0); + we: in std_logic; + clk: in std_logic; + rst: in std_logic; + odata1: out std_logic_vector(sz-1 downto 0); + odata2: out std_logic_vector(sz-1 downto 0) +); +end regfile_ext; + +architecture behav of regfile_ext is + +signal arrsz: natural := 8; +type regarr is array(0 to arrsz-1) of std_logic_vector(sz-1 downto 0); +-- Empty register array used for initialized when rst = 1. +signal s_init: regarr := (others => (others => '0')); +signal regf: regarr; + +begin + process (clk) begin + if (rst = '1') then + regf <= s_init; + elsif (clk'event and clk = '0') then + if (we = '1') then + regf(to_integer(unsigned(waddr))) <= idata; + end if; + end if; + end process; + odata1 <= regf(to_integer(unsigned(raddr1))); + odata2 <= regf(to_integer(unsigned(raddr2))); +end behav; diff --git a/vhdl_digital_design/project/part5_regfile/regfile_ext_tb.vhd b/vhdl_digital_design/project/part5_regfile/regfile_ext_tb.vhd @@ -0,0 +1,107 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity regfile_ext_tb is +end regfile_ext_tb; + +architecture behav of regfile_ext_tb is + +component regfile_ext is +generic ( + sz: natural := 4; + addrw: natural := 2 +); +port ( + idata: in std_logic_vector(sz-1 downto 0); + raddr1: in std_logic_vector(addrw-1 downto 0); + raddr2: in std_logic_vector(addrw-1 downto 0); + waddr: in std_logic_vector(addrw-1 downto 0); + we: in std_logic; + clk: in std_logic; + rst: in std_logic; + odata1: out std_logic_vector(sz-1 downto 0); + odata2: out std_logic_vector(sz-1 downto 0) +); +end component; + +signal s_sz: natural := 4; +signal s_addrw: natural := 2; +signal s_idata: std_logic_vector(s_sz-1 downto 0); +signal s_raddr1: std_logic_vector(s_addrw-1 downto 0); +signal s_raddr2: std_logic_vector(s_addrw-1 downto 0); +signal s_waddr: std_logic_vector(s_addrw-1 downto 0); +signal s_we: std_logic; +signal s_clk: std_logic; +signal s_rst: std_logic; +signal s_odata1: std_logic_vector(s_sz-1 downto 0); +signal s_odata2: std_logic_vector(s_sz-1 downto 0); + +begin + uut: regfile_ext port map ( + idata => s_idata, + raddr1 => s_raddr1, + raddr2 => s_raddr2, + waddr => s_waddr, + we => s_we, + clk => s_clk, + rst => s_rst, + odata1 => s_odata1, + odata2 => s_odata2 + ); + + process begin + s_we <= '1'; + s_clk <= '0'; + s_rst <= '1'; + wait for 250 ns; + + s_clk <= '1'; + s_rst <= '0'; + s_waddr <= "00"; + s_idata <= "0101"; + wait for 250 ns; + + s_clk <= '0'; + wait for 250 ns; + + s_clk <= '1'; + s_waddr <= "01"; + s_idata <= "1101"; + wait for 250 ns; + + s_clk <= '0'; + wait for 250 ns; + + s_clk <= '1'; + s_rst <= '0'; + s_waddr <= "10"; + s_idata <= "0010"; + wait for 250 ns; + + s_clk <= '0'; + wait for 250 ns; + + s_clk <= '1'; + s_waddr <= "11"; + s_idata <= "1001"; + wait for 250 ns; + + s_clk <= '0'; + wait for 250 ns; + + s_we <= '0'; + s_clk <= '1'; + s_raddr1 <= "00"; + s_raddr2 <= "10"; + wait for 250 ns; + + s_clk <= '0'; + wait for 250 ns; + + s_we <= '0'; + s_clk <= '1'; + s_raddr1 <= "01"; + s_raddr2 <= "10"; + wait for 250 ns; + end process; +end behav; diff --git a/vhdl_digital_design/project/part5_regfile/regfile_tb.vhd b/vhdl_digital_design/project/part5_regfile/regfile_tb.vhd @@ -0,0 +1,75 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity regfile_tb is +end regfile_tb; + +architecture behav of regfile_tb is + +component regfile is +generic ( + sz: natural := 4; + addrw: natural := 3 +); +port ( + idata: in std_logic_vector(sz-1 downto 0); + addr: in std_logic_vector(addrw-1 downto 0); + we: in std_logic; + clk: in std_logic; + odata: out std_logic_vector(sz-1 downto 0) +); +end component; + +signal s_sz: natural := 4; +signal s_addrw: natural := 3; +signal s_idata: std_logic_vector(s_sz-1 downto 0); +signal s_addr: std_logic_vector(s_addrw-1 downto 0); +signal s_we: std_logic; +signal s_clk: std_logic; +signal s_odata: std_logic_vector(s_sz-1 downto 0); + +begin + uut: regfile port map ( + idata => s_idata, + addr => s_addr, + we => s_we, + clk => s_clk, + odata => s_odata + ); + + process begin + s_we <= '1'; + s_clk <= '0'; + wait for 250 ns; + + s_clk <= '1'; + s_addr <= "000"; + s_idata <= "0101"; + wait for 250 ns; + + s_clk <= '0'; + wait for 250 ns; + + s_clk <= '1'; + s_addr <= "001"; + s_idata <= "1101"; + wait for 250 ns; + + s_clk <= '0'; + wait for 250 ns; + + s_clk <= '1'; + s_addr <= "010"; + s_idata <= "0010"; + wait for 250 ns; + + s_clk <= '0'; + wait for 250 ns; + + s_clk <= '1'; + s_addr <= "011"; + s_idata <= "1001"; + wait for 250 ns; + end process; +end behav; +