commit 52ce0098f86ac38367b6c68ca71ae49243ae4b6f parent 6c5235ba8853e1e030fc72fe8c38f1af53e59cf8 Author: Christos Margiolis <christos@margiolis.net> Date: Wed, 14 Jul 2021 18:47:24 +0300 more stuff Diffstat:
20 files changed, 502 insertions(+), 73 deletions(-)
diff --git a/vhdl_digital_design/Makefile b/vhdl_digital_design/Makefile @@ -1,6 +1,6 @@ all: - ghdl -a ${IN}.vhd - ghdl -e ${IN} + ghdl -a -fsynopsys ${IN}.vhd + ghdl -e -fsynopsys ${IN} ghdl -r ${IN} --vcd=${IN}.vcd sim: diff --git a/vhdl_digital_design/project/part0_mux_dec/mux2to1gen_tb.png b/vhdl_digital_design/project/part0_mux_dec/mux2to1gen_tb.png Binary files differ. diff --git a/vhdl_digital_design/project/part1_alu/alu_tb.png b/vhdl_digital_design/project/part1_alu/alu_tb.png Binary files differ. diff --git a/vhdl_digital_design/project/part2_alu_ctrl/alu.vhd b/vhdl_digital_design/project/part2_alu_ctrl/alu.vhd @@ -0,0 +1,35 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity alu is +generic ( + dw: natural := 4 +); +port ( + alu_in1: in std_logic_vector(dw-1 downto 0); + alu_in2: in std_logic_vector(dw-1 downto 0); + alu_ctrl: in std_logic_vector(3 downto 0); + alu_out: out std_logic_vector(dw-1 downto 0); + alu_zero: out std_logic +); +end alu; + +architecture behav of alu is +signal sig: std_logic_vector(dw-1 downto 0); + +begin + process (alu_ctrl) begin + case alu_ctrl is + when "0000" => sig <= alu_in1 and alu_in2; + when "0001" => sig <= alu_in1 or alu_in2; + when "0010" => + sig <= std_logic_vector(signed(alu_in1) + signed(alu_in2)); + when "0110" => + sig <= std_logic_vector(signed(alu_in1) - signed(alu_in2)); + when others => sig <= (others => 'X'); + end case; + end process; + alu_zero <= '1' when sig = "0000" else '0'; + alu_out <= sig; +end behav; diff --git a/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl.vhd b/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl.vhd @@ -2,12 +2,18 @@ library ieee; use ieee.std_logic_1164.all; entity alu_ctrl is port ( - op_5to0: in std_logic_vector(5 downto 0); - op_alu: in std_logic_vector(1 downto 0); + funct: in std_logic_vector(5 downto 0); + alu_op: in std_logic_vector(1 downto 0); op: out std_logic_vector(3 downto 0) ); end alu_ctrl; architecture dataflow of alu_ctrl is begin -end behav; + op <= "0010" when (alu_op = "00" or (alu_op = "10" and funct = "100000")) else + "0110" when (alu_op = "01" or (alu_op = "10" and funct = "100010")) else + "0000" when (alu_op = "10" and funct = "100100") else + "0001" when (alu_op = "10" and funct = "100101") else + "0111" when (alu_op = "10" and funct = "101010") else + "1111"; +end dataflow; diff --git a/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl_tb.vhd b/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl_tb.vhd @@ -6,55 +6,55 @@ end alu_ctrl_tb; architecture behav of alu_ctrl_tb is -signal s_op_5to0: std_logic_vector(5 downto 0); -signal s_op_alu: std_logic_vector(1 downto 0); +signal s_funct: std_logic_vector(5 downto 0); +signal s_alu_op: std_logic_vector(1 downto 0); signal s_op: std_logic_vector(3 downto 0); component alu_ctrl is port ( - op_5to0: in std_logic_vector(5 downto 0); - op_alu: in std_logic_vector(1 downto 0); + funct: in std_logic_vector(5 downto 0); + alu_op: in std_logic_vector(1 downto 0); op: out std_logic_vector(3 downto 0) ); end component; begin uut: alu_ctrl port map ( - op_5to0 => s_op_5to0, - op_alu => s_op_alu, + funct => s_funct, + alu_op => s_alu_op, op => s_op ); - process begin; - s_op_alu <= "00"; - s_op_5to0 <= "001001"; + process begin + s_alu_op <= "00"; + s_funct <= "001001"; wait for 250 ns; - s_op_alu <= "00"; - s_op_5to0 <= "001010"; + s_alu_op <= "00"; + s_funct <= "001010"; wait for 250 ns; - s_op_alu <= "01"; - s_op_5to0 <= "100111"; + s_alu_op <= "01"; + s_funct <= "100111"; wait for 250 ns; - s_op_alu <= "10"; - s_op_5to0 <= "100000"; + s_alu_op <= "10"; + s_funct <= "100000"; wait for 250 ns; - s_op_alu <= "10"; - s_op_5to0 <= "100010"; + s_alu_op <= "10"; + s_funct <= "100010"; wait for 250 ns; - s_op_alu <= "10"; - s_op_5to0 <= "100100"; + s_alu_op <= "10"; + s_funct <= "100100"; wait for 250 ns; - s_op_alu <= "10"; - s_op_5to0 <= "100101"; + s_alu_op <= "10"; + s_funct <= "100101"; wait for 250 ns; - s_op_alu <= "10"; - s_op_5to0 <= "101010"; + s_alu_op <= "10"; + s_funct <= "101010"; wait for 250 ns; end process; end behav; diff --git a/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl_test_alu.vhd b/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl_test_alu.vhd @@ -5,23 +5,23 @@ entity alu_ctrl_test_alu is generic ( t_dw: natural := 4 ); port ( - t_op_5to0: in std_logic_vector(5 downto 0); - t_op_alu: in std_logic_vector(1 downto 0); - t_op: in std_logic_vector(3 downto 0); - t_alu_in1: in std_logic_vector(dw-1 downto 0); - t_alu_in2: in std_logic_vector(dw-1 downto 0); - t_alu_ctrl: out std_logic_vector(3 downto 0); - t_alu_out: out std_logic_vector(dw-1 downto 0); + t_funct: in std_logic_vector(5 downto 0); + t_alu_op: in std_logic_vector(1 downto 0); + t_alu_in1: in std_logic_vector(t_dw-1 downto 0); + t_alu_in2: in std_logic_vector(t_dw-1 downto 0); + t_alu_out: out std_logic_vector(t_dw-1 downto 0); t_alu_zero: out std_logic ); end alu_ctrl_test_alu; architecture struct of alu_ctrl_test_alu is +signal s_ctrl: std_logic_vector(3 downto 0); + component alu_ctrl is port ( - op_5to0: in std_logic_vector(5 downto 0); - op_alu: in std_logic_vector(1 downto 0); - op: in std_logic_vector(3 downto 0) + funct: in std_logic_vector(5 downto 0); + alu_op: in std_logic_vector(1 downto 0); + op: out std_logic_vector(3 downto 0) ); end component; @@ -39,15 +39,15 @@ end component; begin uut_alu_ctrl: alu_ctrl port map ( - op_5to0 => t_op_5to0, - op_alu => t_op_alu, - op => t_op + funct => t_funct, + alu_op => t_alu_op, + op => s_ctrl ); uut_alu: alu port map ( alu_in1 => t_alu_in1, alu_in2 => t_alu_in2, - alu_ctrl => t_alu_ctrl, + alu_ctrl => s_ctrl, alu_out => t_alu_out, alu_zero => t_alu_zero ); diff --git a/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl_test_alu_tb.vhd b/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl_test_alu_tb.vhd @@ -7,12 +7,10 @@ end alu_ctrl_test_alu_tb; architecture behav of alu_ctrl_test_alu_tb is signal s_dw: natural := 4; -signal s_t_op_5to0: std_logic_vector(5 downto 0); -signal s_t_op_alu: std_logic_vector(1 downto 0); -signal s_t_op: std_logic_vector(3 downto 0); +signal s_t_funct: std_logic_vector(5 downto 0); +signal s_t_alu_op: std_logic_vector(1 downto 0); signal s_t_alu_in1: std_logic_vector(s_dw-1 downto 0); signal s_t_alu_in2: std_logic_vector(s_dw-1 downto 0); -signal s_t_alu_ctrl std_logic_vector(3 downto 0); signal s_t_alu_out: std_logic_vector(s_dw-1 downto 0); signal s_t_alu_zero: std_logic; @@ -20,25 +18,21 @@ component alu_ctrl_test_alu is generic ( t_dw: natural := 4 ); port ( - t_op_5to0: in std_logic_vector(5 downto 0); - t_op_alu: in std_logic_vector(1 downto 0); - t_op: in std_logic_vector(3 downto 0); - t_alu_in1: in std_logic_vector(dw-1 downto 0); - t_alu_in2: in std_logic_vector(dw-1 downto 0); - t_alu_ctrl: out std_logic_vector(3 downto 0); - t_alu_out: out std_logic_vector(dw-1 downto 0); + t_funct: in std_logic_vector(5 downto 0); + t_alu_op: in std_logic_vector(1 downto 0); + t_alu_in1: in std_logic_vector(t_dw-1 downto 0); + t_alu_in2: in std_logic_vector(t_dw-1 downto 0); + t_alu_out: out std_logic_vector(t_dw-1 downto 0); t_alu_zero: out std_logic ); end component; begin uut: alu_ctrl_test_alu port map ( - t_op_5to0 => s_t_op_5to0, - t_op_alu => s_t_op_alu, - t_op => s_t_op, + t_funct => s_t_funct, + t_alu_op => s_t_alu_op, t_alu_in1 => s_t_alu_in1, t_alu_in2 => s_t_alu_in2, - t_alu_ctrl => s_t_alu_ctrl, t_alu_out => s_t_alu_out, t_alu_zero => s_t_alu_zero ); @@ -47,36 +41,36 @@ begin s_t_alu_in1 <= "1100"; s_t_alu_in2 <= "1100"; - s_t_op_alu <= "00"; - s_t_op_5to0 <= "001001"; + s_t_alu_op <= "00"; + s_t_funct <= "001001"; wait for 250 ns; - s_t_op_alu <= "00"; - s_t_op_5to0 <= "001010"; + s_t_alu_op <= "00"; + s_t_funct <= "001010"; wait for 250 ns; - s_t_op_alu <= "01"; - s_t_op_5to0 <= "100111"; + s_t_alu_op <= "01"; + s_t_funct <= "100111"; wait for 250 ns; - s_t_op_alu <= "10"; - s_t_op_5to0 <= "100000"; + s_t_alu_op <= "10"; + s_t_funct <= "100000"; wait for 250 ns; - s_t_op_alu <= "10"; - s_t_op_5to0 <= "100010"; + s_t_alu_op <= "10"; + s_t_funct <= "100010"; wait for 250 ns; - s_t_op_alu <= "10"; - s_t_op_5to0 <= "100100"; + s_t_alu_op <= "10"; + s_t_funct <= "100100"; wait for 250 ns; - s_t_op_alu <= "10"; - s_t_op_5to0 <= "100101"; + s_t_alu_op <= "10"; + s_t_funct <= "100101"; wait for 250 ns; - s_t_op_alu <= "10"; - s_t_op_5to0 <= "101010"; + s_t_alu_op <= "10"; + s_t_funct <= "101010"; wait for 250 ns; end process; end behav; diff --git a/vhdl_digital_design/project/part3_ctrl_signext_lshift/ctrl.vhd b/vhdl_digital_design/project/part3_ctrl_signext_lshift/ctrl.vhd @@ -0,0 +1,30 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ctrl is port ( + funct: in std_logic_vector(5 downto 0); + reg_dst: out std_logic; + reg_wr: out std_logic; + alu_src: out std_logic; + branch: out std_logic; + mem_rd: out std_logic; + mem_wr: out std_logic; + mem_toreg: out std_logic; + alu_op: out std_logic_vector(1 downto 0) +); +end ctrl; + +architecture dataflow of ctrl is +begin + reg_dst <= '1' when funct = "000000" else '0'; + reg_wr <= '1' when funct = "000000" or funct = "100011" else '0'; + alu_src <= '1' when funct = "100011" or funct = "101011" else '0'; + branch <= '1' when funct = "000100" else '0'; + mem_rd <= '1' when funct = "100011" else '0'; + mem_wr <= '1' when funct = "101011" else '0'; + mem_toreg <= '1' when funct = "100011" else '0'; + with funct select + alu_op <= "10" when "000000", + "01" when "000100", + "00" when others; +end dataflow; diff --git a/vhdl_digital_design/project/part3_ctrl_signext_lshift/ctrl_tb.vhd b/vhdl_digital_design/project/part3_ctrl_signext_lshift/ctrl_tb.vhd @@ -0,0 +1,58 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ctrl_tb is +end ctrl_tb; + +architecture behav of ctrl_tb is + +signal s_funct: std_logic_vector(5 downto 0); +signal s_reg_dst: std_logic; +signal s_reg_wr: std_logic; +signal s_alu_src: std_logic; +signal s_branch: std_logic; +signal s_mem_rd: std_logic; +signal s_mem_wr: std_logic; +signal s_mem_toreg: std_logic; +signal s_alu_op: std_logic_vector(1 downto 0); + +component ctrl is port ( + funct: in std_logic_vector(5 downto 0); + reg_dst: out std_logic; + reg_wr: out std_logic; + alu_src: out std_logic; + branch: out std_logic; + mem_rd: out std_logic; + mem_wr: out std_logic; + mem_toreg: out std_logic; + alu_op: out std_logic_vector(1 downto 0) +); +end component; + +begin + uut: ctrl port map ( + funct => s_funct, + reg_dst => s_reg_dst, + reg_wr => s_reg_wr, + alu_src => s_alu_src, + branch => s_branch, + mem_rd => s_mem_rd, + mem_wr => s_mem_wr, + mem_toreg => s_mem_toreg, + alu_op => s_alu_op + ); + + process begin + s_funct <= "000000"; + wait for 250 ns; + + s_funct <= "100011"; + wait for 250 ns; + + s_funct <= "101011"; + wait for 250 ns; + + s_funct <= "000100"; + wait for 250 ns; + end process; +end behav; diff --git a/vhdl_digital_design/project/part3_ctrl_signext_lshift/shl2.vhd b/vhdl_digital_design/project/part3_ctrl_signext_lshift/shl2.vhd @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity shl2 is port ( + in1: in std_logic_vector(31 downto 0); + d: out std_logic_vector(31 downto 0) +); +end shl2; + +architecture dataflow of shl2 is +begin + d <= in1(29 downto 0) & "00"; +end dataflow; diff --git a/vhdl_digital_design/project/part3_ctrl_signext_lshift/shl2_tb.vhd b/vhdl_digital_design/project/part3_ctrl_signext_lshift/shl2_tb.vhd @@ -0,0 +1,31 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity shl2_tb is +end shl2_tb; + +architecture behav of shl2_tb is + +signal s_in1: std_logic_vector(31 downto 0); +signal s_d: std_logic_vector(31 downto 0); + +component shl2 is port ( + in1: in std_logic_vector(31 downto 0); + d: out std_logic_vector(31 downto 0) +); +end component; + +begin + uut: shl2 port map ( + in1 => s_in1, + d => s_d + ); + + process begin + s_in1 <= x"0000aaaf"; + wait for 250 ns; + + s_in1 <= x"ffffaaaf"; + wait for 250 ns; + end process; +end behav; diff --git a/vhdl_digital_design/project/part3_ctrl_signext_lshift/sign_ext.vhd b/vhdl_digital_design/project/part3_ctrl_signext_lshift/sign_ext.vhd @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity sign_ext is port ( + instr: in std_logic_vector(15 downto 0); + sign_ex: out std_logic_vector(31 downto 0) +); +end sign_ext; + +architecture dataflow of sign_ext is +begin + -- Check the MSB to determine the sign. + sign_ex <= x"0000" & instr when instr(15) = '0' else + x"ffff" & instr when instr(15) = '1'; +end dataflow; diff --git a/vhdl_digital_design/project/part3_ctrl_signext_lshift/sign_ext_tb.vhd b/vhdl_digital_design/project/part3_ctrl_signext_lshift/sign_ext_tb.vhd @@ -0,0 +1,34 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity sign_ext_tb is +end sign_ext_tb; + +architecture behav of sign_ext_tb is + +signal s_instr: std_logic_vector(15 downto 0); +signal s_sign_ex: std_logic_vector(31 downto 0); + +component sign_ext is port ( + instr: in std_logic_vector(15 downto 0); + sign_ex: out std_logic_vector(31 downto 0) +); +end component; + +begin + uut: sign_ext port map ( + instr => s_instr, + sign_ex => s_sign_ex + ); + + process begin + s_instr <= x"0010"; + wait for 250 ns; + + s_instr <= x"1001"; + wait for 250 ns; + + s_instr <= x"80a0"; + wait for 250 ns; + end process; +end behav; diff --git a/vhdl_digital_design/project/part4_instrmem/Makefile b/vhdl_digital_design/project/part4_instrmem_datamem/Makefile diff --git a/vhdl_digital_design/project/part4_instrmem_datamem/datamem.vhd b/vhdl_digital_design/project/part4_instrmem_datamem/datamem.vhd @@ -0,0 +1,32 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity datamem is port ( + clk: in std_logic; + addr: in std_logic_vector(5 downto 0); + we: in std_logic; + re: in std_logic; + writed: in std_logic_vector(31 downto 0); + readd: out std_logic_vector(31 downto 0) +); +end datamem; + +architecture behav of datamem is + +type data_arr is array(0 to 63) of std_logic_vector(31 downto 0); +signal memfile: data_arr; + +begin + process (clk) begin + if (clk'event and clk = '0') then + if we = '1' then + memfile(to_integer(unsigned(addr))) <= writed; + end if; + end if; + if re = '1' then + readd <= memfile(to_integer(unsigned(addr))); + end if; + end process; +end behav; diff --git a/vhdl_digital_design/project/part4_instrmem_datamem/datamem_tb.vhd b/vhdl_digital_design/project/part4_instrmem_datamem/datamem_tb.vhd @@ -0,0 +1,105 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity datamem_tb is +end datamem_tb; + +architecture behav of datamem_tb is + +signal s_clk: std_logic; +signal s_addr: std_logic_vector(5 downto 0); +signal s_we: std_logic; +signal s_re: std_logic; +signal s_writed: std_logic_vector(31 downto 0); +signal s_readd: std_logic_vector(31 downto 0); + +component datamem is port ( + clk: in std_logic; + addr: in std_logic_vector(5 downto 0); + we: in std_logic; + re: in std_logic; + writed: in std_logic_vector(31 downto 0); + readd: out std_logic_vector(31 downto 0) +); +end component; + +begin + uut: datamem port map ( + clk => s_clk, + addr => s_addr, + we => s_we, + re => s_re, + writed => s_writed, + readd => s_readd + ); + + process begin + s_clk <= '0'; + wait for 250 ns; + + s_clk <= '1'; + wait for 250 ns; + + s_we <= '1'; + s_re <= '0'; + s_addr <= "000000"; + s_writed <= "01010101010101010101010101010101"; + wait for 250 ns; + + s_clk <= '0'; + wait for 250 ns; + + s_clk <= '1'; + wait for 250 ns; + + s_addr <= "000001"; + s_writed <= "11011101110111011101110111011101"; + wait for 250 ns; + + s_clk <= '0'; + wait for 250 ns; + + s_clk <= '1'; + wait for 250 ns; + + s_addr <= "000010"; + s_writed <= "00100010001000100010001000100010"; + wait for 250 ns; + + s_clk <= '0'; + wait for 250 ns; + + s_clk <= '1'; + wait for 250 ns; + + s_addr <= "000011"; + s_writed <= "10011001100110011001100110011001"; + wait for 250 ns; + + s_clk <= '0'; + wait for 250 ns; + + s_clk <= '1'; + wait for 250 ns; + + s_we <= '0'; + s_re <= '1'; + s_addr <= "000000"; + wait for 250 ns; + + s_clk <= '0'; + wait for 250 ns; + + s_clk <= '1'; + wait for 250 ns; + + s_addr <= "000001"; + wait for 250 ns; + + s_clk <= '0'; + wait for 250 ns; + + s_clk <= '1'; + wait for 250 ns; + end process; +end behav; diff --git a/vhdl_digital_design/project/part4_instrmem_datamem/instrmem.vhd b/vhdl_digital_design/project/part4_instrmem_datamem/instrmem.vhd @@ -0,0 +1,36 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity instrmem is port ( + addr: in std_logic_vector(3 downto 0); + c: out std_logic_vector(31 downto 0) +); +end instrmem; + +architecture dataflow of instrmem is + +type instr_arr is array(0 to 15) of std_logic_vector (31 downto 0); +constant instr_mem: instr_arr := ( + "11111111111111111111111111111111", -- 0 + "10001010100101010101000011101111", -- 1 + "11111111111111111111111111111111", -- 2 + "00000000000000000000000000000000", -- 3 + "11111111111111111111111111111111", -- 4 + "00000000000000000000000000000000", -- 5 + "00000000101001100010000000100000", -- 6 + "11111111111111111111111111111111", -- 7 + "11111111111111111111111111111111", -- 8 + "11111111111111111111111111111111", -- 9 + "10101010101011110000101110001010", -- 10 + "11111111111111100000000000000000", -- 11 + "10001011101010111010111101010111", -- 12 + "11111111111111111111111111111111", -- 13 + "10110111000111010101010101111111", -- 14 + "11111111111111111111111111111111" -- 15 +); + +begin + c <= instr_mem(to_integer(unsigned(addr))); +end dataflow; diff --git a/vhdl_digital_design/project/part4_instrmem_datamem/instrmem_tb.vhd b/vhdl_digital_design/project/part4_instrmem_datamem/instrmem_tb.vhd @@ -0,0 +1,40 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity instrmem_tb is +end instrmem_tb; + +architecture behav of instrmem_tb is + +signal s_addr: std_logic_vector(3 downto 0); +signal s_c: std_logic_vector(31 downto 0); + +component instrmem is port ( + addr: in std_logic_vector(3 downto 0); + c: out std_logic_vector(31 downto 0) +); +end component; + +begin + uut: instrmem port map ( + addr => s_addr, + c => s_c + ); + + process begin + s_addr <= "0001"; + wait for 250 ns; + + s_addr <= "0010"; + wait for 250 ns; + + s_addr <= "0110"; + wait for 250 ns; + + s_addr <= "1000"; + wait for 250 ns; + + s_addr <= "1010"; + wait for 250 ns; + end process; +end behav; diff --git a/vhdl_digital_design/project/part6_mips/Makefile b/vhdl_digital_design/project/part6_mips_r_ops/Makefile
