commit 6c5235ba8853e1e030fc72fe8c38f1af53e59cf8 parent ae6a0818a233734bb79a28ff653695f629c58828 Author: Christos Margiolis <christos@margiolis.net> Date: Sun, 11 Jul 2021 19:43:31 +0300 i need to get done with these Diffstat:
21 files changed, 309 insertions(+), 100 deletions(-)
diff --git a/vhdl_digital_design/project/part0/Makefile b/vhdl_digital_design/project/part0_mux_dec/Makefile diff --git a/vhdl_digital_design/project/part0/dec2to4.vhd b/vhdl_digital_design/project/part0_mux_dec/dec2to4.vhd diff --git a/vhdl_digital_design/project/part0/mux2to1.vhd b/vhdl_digital_design/project/part0_mux_dec/mux2to1.vhd diff --git a/vhdl_digital_design/project/part0/mux2to1gen.vhd b/vhdl_digital_design/project/part0_mux_dec/mux2to1gen.vhd diff --git a/vhdl_digital_design/project/part0/mux2to1gen_tb.png b/vhdl_digital_design/project/part0_mux_dec/mux2to1gen_tb.png Binary files differ. diff --git a/vhdl_digital_design/project/part0/mux2to1gen_tb.vhd b/vhdl_digital_design/project/part0_mux_dec/mux2to1gen_tb.vhd diff --git a/vhdl_digital_design/project/part1/alu.vhd b/vhdl_digital_design/project/part1/alu.vhd @@ -1,35 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity alu is -generic ( - dw: natural := 4 -); -port ( - alu_in1: in std_logic_vector(dw-1 downto 0); - alu_in2: in std_logic_vector(dw-1 downto 0); - alu_ctrl: in std_logic_vector(3 downto 0); - alu_out: out std_logic_vector(dw-1 downto 0); - alu_zero: out std_logic -); -end alu; - -architecture behav of alu is -signal sig: std_logic_vector(dw-1 downto 0); - -begin - process (alu_ctrl) begin - case alu_ctrl is - when "0000" => sig <= alu_in1 and alu_in2; - when "0001" => sig <= alu_in1 or alu_in2; - when "0010" => - sig <= std_logic_vector(signed(alu_in1) + signed(alu_in2)); - when "0110" => - sig <= std_logic_vector(signed(alu_in1) - signed(alu_in2)); - when others => sig <= (others => 'X'); - end case; - end process; - alu_zero <= '1' when sig = "0000" else '0'; - alu_out <= sig; -end behav; diff --git a/vhdl_digital_design/project/part1/alu_tb.vhd b/vhdl_digital_design/project/part1/alu_tb.vhd @@ -1,65 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity alu_tb is -end alu_tb; - -architecture behav of alu_tb is - -signal s_dw: natural := 4; -signal s_alu_in1: std_logic_vector(s_dw-1 downto 0); -signal s_alu_in2: std_logic_vector(s_dw-1 downto 0); -signal s_alu_ctrl: std_logic_vector(3 downto 0); -signal s_alu_out: std_logic_vector(s_dw-1 downto 0); -signal s_alu_zero: std_logic; - -component alu is -generic ( - dw: natural := 4 -); -port ( - alu_in1: in std_logic_vector(dw-1 downto 0); - alu_in2: in std_logic_vector(dw-1 downto 0); - alu_ctrl: in std_logic_vector(3 downto 0); - alu_out: out std_logic_vector(dw-1 downto 0); - alu_zero: out std_logic -); -end component; - -begin - uut: alu port map ( - alu_in1 => s_alu_in1, - alu_in2 => s_alu_in2, - alu_ctrl => s_alu_ctrl, - alu_out => s_alu_out, - alu_zero => s_alu_zero - ); - - process begin - s_alu_in1 <= "0010"; - s_alu_in2 <= "0100"; - s_alu_ctrl <= "0010"; - wait for 250 ns; - - s_alu_in1 <= "0100"; - s_alu_in2 <= "1111"; - s_alu_ctrl <= "0000"; - wait for 250 ns; - - s_alu_in1 <= "0100"; - s_alu_in2 <= "1111"; - s_alu_ctrl <= "0001"; - wait for 250 ns; - - s_alu_in1 <= "0100"; - s_alu_in2 <= "0010"; - s_alu_ctrl <= "0110"; - wait for 250 ns; - - s_alu_in1 <= "0100"; - s_alu_in2 <= "0110"; - s_alu_ctrl <= "0110"; - wait for 250 ns; - end process; -end behav; diff --git a/vhdl_digital_design/project/part1/Makefile b/vhdl_digital_design/project/part1_alu/Makefile diff --git a/vhdl_digital_design/project/part1_alu/alu.vhd b/vhdl_digital_design/project/part1_alu/alu.vhd @@ -0,0 +1,35 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity alu is +generic ( + dw: natural := 4 +); +port ( + alu_in1: in std_logic_vector(dw-1 downto 0); + alu_in2: in std_logic_vector(dw-1 downto 0); + alu_ctrl: in std_logic_vector(3 downto 0); + alu_out: out std_logic_vector(dw-1 downto 0); + alu_zero: out std_logic +); +end alu; + +architecture behav of alu is +signal sig: std_logic_vector(dw-1 downto 0); + +begin + process (alu_ctrl) begin + case alu_ctrl is + when "0000" => sig <= alu_in1 and alu_in2; + when "0001" => sig <= alu_in1 or alu_in2; + when "0010" => + sig <= std_logic_vector(signed(alu_in1) + signed(alu_in2)); + when "0110" => + sig <= std_logic_vector(signed(alu_in1) - signed(alu_in2)); + when others => sig <= (others => 'X'); + end case; + end process; + alu_zero <= '1' when sig = "0000" else '0'; + alu_out <= sig; +end behav; diff --git a/vhdl_digital_design/project/part1/alu_tb.png b/vhdl_digital_design/project/part1_alu/alu_tb.png Binary files differ. diff --git a/vhdl_digital_design/project/part1_alu/alu_tb.vhd b/vhdl_digital_design/project/part1_alu/alu_tb.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity alu_tb is +end alu_tb; + +architecture behav of alu_tb is + +signal s_dw: natural := 4; +signal s_alu_in1: std_logic_vector(s_dw-1 downto 0); +signal s_alu_in2: std_logic_vector(s_dw-1 downto 0); +signal s_alu_ctrl: std_logic_vector(3 downto 0); +signal s_alu_out: std_logic_vector(s_dw-1 downto 0); +signal s_alu_zero: std_logic; + +component alu is +generic ( + dw: natural := 4 +); +port ( + alu_in1: in std_logic_vector(dw-1 downto 0); + alu_in2: in std_logic_vector(dw-1 downto 0); + alu_ctrl: in std_logic_vector(3 downto 0); + alu_out: out std_logic_vector(dw-1 downto 0); + alu_zero: out std_logic +); +end component; + +begin + uut: alu port map ( + alu_in1 => s_alu_in1, + alu_in2 => s_alu_in2, + alu_ctrl => s_alu_ctrl, + alu_out => s_alu_out, + alu_zero => s_alu_zero + ); + + process begin + s_alu_in1 <= "0010"; + s_alu_in2 <= "0100"; + s_alu_ctrl <= "0010"; + wait for 250 ns; + + s_alu_in1 <= "0100"; + s_alu_in2 <= "1111"; + s_alu_ctrl <= "0000"; + wait for 250 ns; + + s_alu_in1 <= "0100"; + s_alu_in2 <= "1111"; + s_alu_ctrl <= "0001"; + wait for 250 ns; + + s_alu_in1 <= "0100"; + s_alu_in2 <= "0010"; + s_alu_ctrl <= "0110"; + wait for 250 ns; + + s_alu_in1 <= "0100"; + s_alu_in2 <= "0110"; + s_alu_ctrl <= "0110"; + wait for 250 ns; + end process; +end behav; diff --git a/vhdl_digital_design/project/part2/Makefile b/vhdl_digital_design/project/part2_alu_ctrl/Makefile diff --git a/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl.vhd b/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl.vhd @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity alu_ctrl is port ( + op_5to0: in std_logic_vector(5 downto 0); + op_alu: in std_logic_vector(1 downto 0); + op: out std_logic_vector(3 downto 0) +); +end alu_ctrl; + +architecture dataflow of alu_ctrl is +begin +end behav; diff --git a/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl_tb.vhd b/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl_tb.vhd @@ -0,0 +1,60 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity alu_ctrl_tb is +end alu_ctrl_tb; + +architecture behav of alu_ctrl_tb is + +signal s_op_5to0: std_logic_vector(5 downto 0); +signal s_op_alu: std_logic_vector(1 downto 0); +signal s_op: std_logic_vector(3 downto 0); + +component alu_ctrl is port ( + op_5to0: in std_logic_vector(5 downto 0); + op_alu: in std_logic_vector(1 downto 0); + op: out std_logic_vector(3 downto 0) +); +end component; + +begin + uut: alu_ctrl port map ( + op_5to0 => s_op_5to0, + op_alu => s_op_alu, + op => s_op + ); + + process begin; + s_op_alu <= "00"; + s_op_5to0 <= "001001"; + wait for 250 ns; + + s_op_alu <= "00"; + s_op_5to0 <= "001010"; + wait for 250 ns; + + s_op_alu <= "01"; + s_op_5to0 <= "100111"; + wait for 250 ns; + + s_op_alu <= "10"; + s_op_5to0 <= "100000"; + wait for 250 ns; + + s_op_alu <= "10"; + s_op_5to0 <= "100010"; + wait for 250 ns; + + s_op_alu <= "10"; + s_op_5to0 <= "100100"; + wait for 250 ns; + + s_op_alu <= "10"; + s_op_5to0 <= "100101"; + wait for 250 ns; + + s_op_alu <= "10"; + s_op_5to0 <= "101010"; + wait for 250 ns; + end process; +end behav; diff --git a/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl_test_alu.vhd b/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl_test_alu.vhd @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity alu_ctrl_test_alu is generic ( + t_dw: natural := 4 +); +port ( + t_op_5to0: in std_logic_vector(5 downto 0); + t_op_alu: in std_logic_vector(1 downto 0); + t_op: in std_logic_vector(3 downto 0); + t_alu_in1: in std_logic_vector(dw-1 downto 0); + t_alu_in2: in std_logic_vector(dw-1 downto 0); + t_alu_ctrl: out std_logic_vector(3 downto 0); + t_alu_out: out std_logic_vector(dw-1 downto 0); + t_alu_zero: out std_logic +); +end alu_ctrl_test_alu; + +architecture struct of alu_ctrl_test_alu is + +component alu_ctrl is port ( + op_5to0: in std_logic_vector(5 downto 0); + op_alu: in std_logic_vector(1 downto 0); + op: in std_logic_vector(3 downto 0) +); +end component; + +component alu is generic ( + dw: natural := 4 +); +port ( + alu_in1: in std_logic_vector(dw-1 downto 0); + alu_in2: in std_logic_vector(dw-1 downto 0); + alu_ctrl: in std_logic_vector(3 downto 0); + alu_out: out std_logic_vector(dw-1 downto 0); + alu_zero: out std_logic +); +end component; + +begin + uut_alu_ctrl: alu_ctrl port map ( + op_5to0 => t_op_5to0, + op_alu => t_op_alu, + op => t_op + ); + + uut_alu: alu port map ( + alu_in1 => t_alu_in1, + alu_in2 => t_alu_in2, + alu_ctrl => t_alu_ctrl, + alu_out => t_alu_out, + alu_zero => t_alu_zero + ); +end struct; diff --git a/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl_test_alu_tb.vhd b/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl_test_alu_tb.vhd @@ -0,0 +1,82 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity alu_ctrl_test_alu_tb is +end alu_ctrl_test_alu_tb; + +architecture behav of alu_ctrl_test_alu_tb is + +signal s_dw: natural := 4; +signal s_t_op_5to0: std_logic_vector(5 downto 0); +signal s_t_op_alu: std_logic_vector(1 downto 0); +signal s_t_op: std_logic_vector(3 downto 0); +signal s_t_alu_in1: std_logic_vector(s_dw-1 downto 0); +signal s_t_alu_in2: std_logic_vector(s_dw-1 downto 0); +signal s_t_alu_ctrl std_logic_vector(3 downto 0); +signal s_t_alu_out: std_logic_vector(s_dw-1 downto 0); +signal s_t_alu_zero: std_logic; + +component alu_ctrl_test_alu is generic ( + t_dw: natural := 4 +); +port ( + t_op_5to0: in std_logic_vector(5 downto 0); + t_op_alu: in std_logic_vector(1 downto 0); + t_op: in std_logic_vector(3 downto 0); + t_alu_in1: in std_logic_vector(dw-1 downto 0); + t_alu_in2: in std_logic_vector(dw-1 downto 0); + t_alu_ctrl: out std_logic_vector(3 downto 0); + t_alu_out: out std_logic_vector(dw-1 downto 0); + t_alu_zero: out std_logic +); +end component; + +begin + uut: alu_ctrl_test_alu port map ( + t_op_5to0 => s_t_op_5to0, + t_op_alu => s_t_op_alu, + t_op => s_t_op, + t_alu_in1 => s_t_alu_in1, + t_alu_in2 => s_t_alu_in2, + t_alu_ctrl => s_t_alu_ctrl, + t_alu_out => s_t_alu_out, + t_alu_zero => s_t_alu_zero + ); + + process begin + s_t_alu_in1 <= "1100"; + s_t_alu_in2 <= "1100"; + + s_t_op_alu <= "00"; + s_t_op_5to0 <= "001001"; + wait for 250 ns; + + s_t_op_alu <= "00"; + s_t_op_5to0 <= "001010"; + wait for 250 ns; + + s_t_op_alu <= "01"; + s_t_op_5to0 <= "100111"; + wait for 250 ns; + + s_t_op_alu <= "10"; + s_t_op_5to0 <= "100000"; + wait for 250 ns; + + s_t_op_alu <= "10"; + s_t_op_5to0 <= "100010"; + wait for 250 ns; + + s_t_op_alu <= "10"; + s_t_op_5to0 <= "100100"; + wait for 250 ns; + + s_t_op_alu <= "10"; + s_t_op_5to0 <= "100101"; + wait for 250 ns; + + s_t_op_alu <= "10"; + s_t_op_5to0 <= "101010"; + wait for 250 ns; + end process; +end behav; diff --git a/vhdl_digital_design/project/part3/Makefile b/vhdl_digital_design/project/part3_ctrl_signext_lshift/Makefile diff --git a/vhdl_digital_design/project/part4/Makefile b/vhdl_digital_design/project/part4_instrmem/Makefile diff --git a/vhdl_digital_design/project/part5/Makefile b/vhdl_digital_design/project/part5_regfile/Makefile diff --git a/vhdl_digital_design/project/part6/Makefile b/vhdl_digital_design/project/part6_mips/Makefile
