commit 689708e31e84dcc493b7a38d2f1a01412ebcf210
parent 11aa99766552691933815eba3a31755e933528f9
Author: Christos Margiolis <christos@margiolis.net>
Date: Sun, 18 Jul 2021 04:00:10 +0300
mips ALMOST done
Diffstat:
4 files changed, 151 insertions(+), 2 deletions(-)
diff --git a/vhdl_digital_design/project/part6_mips_r_ops/adder32.vhd b/vhdl_digital_design/project/part6_mips_r_ops/adder32.vhd
@@ -2,10 +2,31 @@ library ieee;
use ieee.std_logic_1164.all;
entity adder32 is port (
+ a: in std_logic_vector(31 downto 0);
+ b: in std_logic_vector(31 downto 0);
+ cin: in std_logic;
+ s: out std_logic_vector(31 downto 0);
+ cout: out std_logic
);
end adder32;
-architecture behav of adder32 is
+architecture struct of adder32 is
+
+component fa is port (
+ a: in std_logic;
+ b: in std_logic;
+ cin: in std_logic;
+ s: out std_logic;
+ cout: out std_logic
+);
+end component;
+
+signal y: std_logic_vector(32 downto 0);
begin
-end behav;
+ y(0) <= cin;
+ cout <= y(32);
+ adder_gen: for i in 0 to 31 generate
+ adder_map: fa port map (a(i), b(i), cin, s(i), cout => y(i+1));
+ end generate;
+end struct;
diff --git a/vhdl_digital_design/project/part6_mips_r_ops/fa.vhd b/vhdl_digital_design/project/part6_mips_r_ops/fa.vhd
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity fa is port (
+ a: in std_logic;
+ b: in std_logic;
+ cin: in std_logic;
+ s: out std_logic;
+ cout: out std_logic
+);
+end fa;
+
+architecture dataflow of fa is
+begin
+ s <= a xor b xor cin;
+ cout <= (a and b) or (cin and (a xor b));
+end dataflow;
diff --git a/vhdl_digital_design/project/part6_mips_r_ops/mips.vhd b/vhdl_digital_design/project/part6_mips_r_ops/mips.vhd
@@ -2,6 +2,15 @@ library ieee;
use ieee.std_logic_1164.all;
entity mips is port (
+ m_clk: in std_logic;
+ m_rst: in std_logic;
+ m_instr: out std_logic_vector(31 downto 0);
+ m_raddr1: out std_logic_vector(4 downto 0);
+ m_raddr2: out std_logic_vector(4 downto 0);
+ m_waddr: out std_logic_vector(4 downto 0);
+ m_reg1: out std_logic_vector(31 downto 0);
+ m_reg2: out std_logic_vector(31 downto 0);
+ m_out: out std_logic_vector(31 downto 0)
);
end mips;
@@ -65,12 +74,103 @@ component alu_ctrl is port (
end component;
component pc is port (
+ clk: in std_logic;
+ rst: in std_logic;
+ ipc: in std_logic_vector(3 downto 0);
+ opc: out std_logic_vector(3 downto 0)
);
end component;
component adder32 is port (
+ a: in std_logic_vector(31 downto 0);
+ b: in std_logic_vector(31 downto 0);
+ cin: in std_logic;
+ s: out std_logic_vector(31 downto 0);
+ cout: out std_logic
);
end component;
+signal s_instr: std_logic_vector(31 downto 0);
+signal s_op: std_logic_vector(3 downto 0);
+signal s_alu_out: std_logic_vector(31 downto 0);
+signal s_alu_zero: std_logic;
+signal s_reg_out1: std_logic_vector(31 downto 0);
+signal s_reg_out2: std_logic_vector(31 downto 0);
+signal s_reg_wr: std_logic;
+signal s_reg_dst: std_logic;
+signal s_alu_src: std_logic;
+signal s_branch: std_logic;
+signal s_mem_rd: std_logic;
+signal s_mem_wr: std_logic;
+signal s_mem_toreg: std_logic;
+signal s_alu_op: std_logic_vector(1 downto 0);
+signal s_opc: std_logic_vector(3 downto 0);
+signal s_adder_to_pc: std_logic_vector(3 downto 0);
+constant c_pc_add_val: std_logic_vector(3 downto 0) := "0100";
+
begin
+ alu_map: alu port map (
+ alu_in1 => s_reg_out1,
+ alu_in2 => s_reg_out2,
+ alu_ctrl => s_op,
+ alu_out => s_alu_out,
+ alu_zero => s_alu_zero
+ );
+
+ regfile_ext_map: regfile_ext port map (
+ idata => s_alu_out,
+ raddr1 => s_instr(25 downto 21),
+ raddr2 => s_instr(20 downto 16),
+ waddr => s_instr(15 downto 11),
+ we => s_reg_wr,
+ clk => m_clk,
+ rst => m_rst,
+ odata1 => s_reg_out1,
+ odata2 => s_reg_out2
+ );
+
+ instrmem_map: instrmem port map (
+ addr => s_opc,
+ c => s_instr
+ );
+
+ ctrl_map: ctrl port map (
+ funct => s_instr(31 downto 26),
+ reg_dst => s_reg_dst,
+ reg_wr => s_reg_wr,
+ alu_src => s_alu_src,
+ branch => s_branch,
+ mem_rd => s_mem_rd,
+ mem_wr => s_mem_wr,
+ mem_toreg => s_mem_toreg,
+ alu_op => s_alu_op
+ );
+
+ alu_ctrl_map: alu_ctrl port map (
+ funct => s_instr(5 downto 0),
+ alu_op => s_alu_op,
+ op => s_op
+ );
+
+
+ pc_map: pc port map (
+ clk => m_clk,
+ rst => m_rst,
+ ipc => s_adder_to_pc,
+ opc => s_opc
+ );
+
+ adder32_map: adder32 port map (
+ a => s_opc,
+ b => c_pc_add_val
+ oval => s_adder_to_pc
+ );
+
+ m_instr <= s_instr;
+ m_raddr1 <= s_instr(25 downto 21);
+ m_raddr2 <= s_instr(20 downto 16);
+ m_waddr <= s_instr(15 downto 11);
+ m_reg1 <= s_reg_out1;
+ m_reg2 <= s_reg_out2;
+ m_out <= s_alu_out;
end struct;
diff --git a/vhdl_digital_design/project/part6_mips_r_ops/pc.vhd b/vhdl_digital_design/project/part6_mips_r_ops/pc.vhd
@@ -2,9 +2,20 @@ library ieee;
use ieee.std_logic_1164.all;
entity pc is port (
+ clk: in std_logic;
+ rst: in std_logic;
+ ipc: in std_logic_vector(3 downto 0);
+ opc: out std_logic_vector(3 downto 0)
);
end pc;
architecture behav of pc is
begin
+ process (clk) begin
+ if (rst = '1') then
+ opc <= "0000";
+ elsif (rising_edge(clk)) then
+ opc <= ipc;
+ end if;
+ end process;
end behav;
