commit a8b94c811e9242936c187a2a0dacd311ad889fa5 parent 89b5525de39b47b99e2aaab1b430e81c487cb39e Author: Christos Margiolis <christos@margiolis.net> Date: Tue, 13 Apr 2021 19:27:57 +0300 new stuff as always Diffstat:
22 files changed, 597 insertions(+), 40 deletions(-)
diff --git a/c-os2/ex1/ex2.c b/c-os2/ex1/ex2.c @@ -93,7 +93,7 @@ main(int argc, char *argv[]) default: /* wait for P2 to exit */ if (wait(NULL) == -1) - die("waitpid"); + die("wait"); } if (execl("/bin/ps", "ps", NULL) == -1) die("execl"); diff --git a/c-os2/ex1/ex3.c b/c-os2/ex1/ex3.c @@ -10,12 +10,55 @@ * Τρόπος μεταγλώττισης: `cc ex3.c -lpthread -o ex3` */ -static char *argv0; +static void *calc(void *); +static void die(const char *); +static char *argv0; /* Program name */ +static int *sums; /* Sums for each thread */ +static int *arr; /* Global vector */ +static int n; /* `arr`'s length */ +static int ntd; /* Number of threads */ +static pthread_mutex_t mutex; /* Mutex to prevent race conditions */ + +/* + * Each thread calculates the sum of the squares of each element in a specified + * region in `arr`. That range is determined by the thread's ID (e.g the current + * thread) and the number of elements that each thread has to compute. Since + * `arr`'s length is a multiple of `ntd`, we can calculate the number of elements + * each thread will compute by doing `n / ntd`. + * + * For example, `ntd = 2` and `n = 4`, and `arr [1, 2, 3, 4]`. + * Each thread will compute `n / ntd = 2` elements. + * + * Thread 0 will operate in the region: + * `td * (n / ntd) = 0 * 2 = 0` to + * `(td + 1) * (n / ntd) - 1 = (0 + 1) * 2 - 1 = 1` + * + * Thread 1 will operate in the region: + * `1 * 2 = 2` to `(1 + 1) * 2 - 1 = 3` + * + * So effectively, each thread will be assigned to compute an equal amount of + * elements. + */ static void * -calcsum(void *tid) +calc(void *tid) { - printf("td: %ld\n", (long)tid); + long td; + int localsum; + int i; + + if (pthread_mutex_lock(&mutex) != 0) + die("pthread_mutex_lock"); + + td = (long)tid; + localsum = 0; + for (i = td * (n / ntd); i < (td + 1) * (n / ntd); i++) { + printf("td: %ld | arr[%d]: %d\n", td, i, arr[i]); + sums[td] += arr[i] * arr[i]; + } + if (pthread_mutex_unlock(&mutex) != 0) + die("pthread_mutex_unlock"); + return NULL; } @@ -30,57 +73,76 @@ die(const char *str) int main(int argc, char *argv[]) { - pthread_t *tds; - FILE *fp; - int *arr; - long i; - long n; - int nt; + pthread_t *tds; /* Threads */ + FILE *fp; /* Either stdin or a text file */ + int totalsum; /* Total sum */ + long i; /* Counter */ argv0 = *argv++; + /* + * If an argument was passed, use it as a file to read from, + * otherwise read from stdin. + */ + if (*argv == NULL) + fp = stdin; + else if ((fp = fopen(*argv, "r")) == NULL) + die("fopen"); + + /* + * We do error checking for `n` and `ntd` but in case we read from a + * file the program might break if the data is wrong (i.e fails the + * error checks at least once) since it will keep going further down + * into the file. The same doesn't apply for when reading from stdin -- + * we can just give it a new number until it's correct. + */ do { - /* we cannot have < 0 threads */ printf("p: "); - scanf("%d", &nt); - } while (nt < 0); + fscanf(fp, "%d", &ntd); + /* Cannot have < 0 threads. */ + } while (ntd < 0); do { - /* make sure `n` is positive and also a multiple of `nt` */ printf("n: "); - scanf("%ld", &n); - } while (n < 0 || n % nt != 0); + fscanf(fp, "%d", &n); + /* Make sure `n` is positive and also a multiple of `ntd`. */ + } while (n < 0 || n % ntd != 0); - if ((tds = malloc(nt * sizeof(pthread_t))) == NULL) + if ((tds = malloc(ntd * sizeof(pthread_t))) == NULL) die("malloc"); - if ((arr = malloc(n * sizeof(int))) == NULL) - die("malloc:"); + die("malloc"); + if ((sums = malloc(ntd * sizeof(int))) == NULL) + die("malloc"); - /* - * if an argument was passed, use it as a file to read from, - * otherwise read from stdin. - */ - if (*argv == NULL) - fp = stdin; - else - if ((fp = fopen(*argv, "r")) == NULL) - die("fopen"); + /* Read the vector. */ for (i = 0; i < n; i++) fscanf(fp, "%d", &arr[i]); (void)fclose(fp); - for (i = 0; i < n; i++) { - if (pthread_create(&tds[i], NULL, calcsum, (void *)i) != 0) + if (pthread_mutex_init(&mutex, NULL) != 0) + die("pthread_mutex_init"); + /* + * Start multithreading. For each thread we assign `calc` + * to be the callback function that each thread will call. + */ + for (i = 0; i < ntd; i++) { + if (pthread_create(&tds[i], NULL, calc, (void *)i) != 0) die("pthread_create"); - /* TODO: :-) */ if (pthread_join(tds[i], NULL) != 0) die("pthread_join"); } - pthread_exit(NULL); + + totalsum = 0; + while (ntd--) + totalsum += *sums++; + printf("total sum: %d\n", totalsum); free(tds); free(arr); + free(sums); + (void)pthread_mutex_destroy(&mutex); + pthread_exit(NULL); return 0; } diff --git a/octave-signals-systems/ex3/doc.pdf b/octave-signals-systems/ex3/doc.pdf Binary files differ. diff --git a/octave-signals-systems/ex3/doc.tex b/octave-signals-systems/ex3/doc.tex @@ -0,0 +1,73 @@ +\documentclass{article} +\usepackage[utf8]{inputenc} +\usepackage[greek,english]{babel} \usepackage{alphabeta} +\usepackage{fancyhdr} +\usepackage{listings} +\usepackage{mathtools} +\usepackage{xcolor} +\usepackage{graphicx} +\usepackage{float} +\usepackage[backend=biber]{biblatex} + +\title{Σήματα και Συστήματα - Εργασία 3} +\author{Χρήστος Μαργιώλης - 19390133} +\date{Απρίλιος 2021} + +\begin{document} + +\begin{titlepage} + \maketitle + \begin{figure}[t!] + \begin{center} + \includegraphics[scale=0.3]{./res/uniwalogo.png} \\ + \Large + \textbf{Πανεπιστήμιο Δυτικής Αττικής} \\ + \large + Τμήμα Μηχανικών Πληροφορικής και Ηλεκτρονικών Υπολογιστών + \end{center} + \end{figure} +\end{titlepage} + +\renewcommand{\contentsname}{Περιεχόμενα} +\tableofcontents + +\section{'Ασκηση 1} + +\begin{itemize} + \item 'Εστω το σήμα ολοκληρωτή που φαίνεται στο παρκάτω + σχήμα (φυλλάδιο άσκηση σελίδα 12). 'Ενα τέτοιο + σύστημα δέχεται ως είσοδο ένα σήμα $x(t)$ και η έξοδος + $y(t)$ δίνεται από την σχέση: + \[y(t) = \int_{-\infty}^{t} x(τ)dτ\] + Σας ζητείται να μελετήσετε αυτό το σύστημα και να + απαντήσετε ως προς τις ιδιότητες: + \begin{itemize} + \item Γραμμικό ή μηγραμμικό. + \item Δυναμικό ή στατικό. + \item Αιτιατό ή μη αιτιατό. + \item Χρονικά αμετάβλητο ή χρονικά μεταβαλλόμενο. + \item Ευσταθές ή ασταθές. + \end{itemize} +\end{itemize} + +<++> + +\section{'Ασκηση 2} + +\begin{itemize} + \item Να εξετάσετε ως προς την ευστάθεια το σύστημα με σχέση + εισόδου-εξόδου $y(t) = e^{x(t)}$. +\end{itemize} + +<++> + +\section{'Ασκηση 3} + +\begin{itemize} + \item Να εξεταστεί εάν το σύστημα που διέπεται από την σχέση + εισόδου-εξόδου $y(t) = x(t/4)$ είναι αιτιατό. +\end{itemize} + +<++> + +\end{document} diff --git a/octave-signals-systems/ex3/res/uniwalogo.png b/octave-signals-systems/ex3/res/uniwalogo.png Binary files differ. diff --git a/sql-databases/ex1/new_personnel.sql b/sql-databases/ex1/new_personnel.sql @@ -0,0 +1,58 @@ +CREATE TABLE DEPT ( + DEPTNO INT(2) NOT NULL, + DNAME VARCHAR, + LOC VARCHAR, + PRIMARY KEY(DEPTNO) +); + +CREATE TABLE EMP ( + EMPNO INT(2) NOT NULL, + ENAME VARCHAR, + JOB VARCHAR, + HIERDATE DATE, + MGR INT(2), + SAL FLOAT(7,2), + COMM FLOAT(7,2), + DEPTNO INT(2) NOT NULL, + PRIMARY KEY(EMPNO), + FOREIGN KEY(DEPTNO) REFERENCES DEPT(DEPTNO) +); + +CREATE TABLE PROJ ( + PROJ_CODE INT(3) NOT NULL, + DESCRIPTION VARCHAR, + PRIMARY KEY(PROJ_CODE) +); + +CREATE TABLE ASSIGN ( + EMPNO INT(2) NOT NULL, + PROJ_CODE INT(3), + A_TIME INT(3), + PRIMARY KEY(EMPNO, PROJ_CODE), + FOREIGN KEY(EMPNO) REFERENCES EMP(EMPNO), + FOREIGN KEY(PROJ_CODE) REFERENCES PROJ(PROJ_CODE) +); + +INSERT INTO DEPT VALUES + (10, 'ACCOUNTING', 'ATHENS'), + (20, 'SALES', 'LONDON'), + (30, 'RESEARCH', 'ATHENS'), + (40, 'PAYROLL', 'LONDON'); + +INSERT INTO EMP VALUES + (10, 'CODD', 'ANALYST', '1/1/89', 15, 3000, NULL, 10), + (15, 'ELMASRI', 'ANALYST', '2/5/95', 15, 1200, 150, 10), + (20, 'NAVATHE', 'SALESMAN', '7/7/77', 20, 2000, NULL, 20), + (30, 'DATE', 'PROGRAMMER', '4/5/04', 15, 1800, 200, 10); + +INSERT INTO PROJ VALUES + (100, 'PAYROLL'), + (200, 'PERSONELL'), + (300, 'SALES'); + +INSERT INTO ASSIGN VALUES + (10, 100, 40), + (10, 200, 60), + (15, 100, 100), + (20, 200, 100), + (30, 100, 100); diff --git a/vhdl-digital-design/Makefile b/vhdl-digital-design/Makefile @@ -1,8 +1,6 @@ all: ghdl -a ${IN}.vhd ghdl -e ${IN} - -vcd: all ghdl -r ${IN} --vcd=${IN}.vcd sim: diff --git a/vhdl-digital-design/ex1/adder4.vhd b/vhdl-digital-design/ex1/adder4.vhd @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; +use work.all; + +entity adder4 is port ( + a, b: in std_logic_vector(3 downto 0); + cin: in std_logic; + s: out std_logic_vector(3 downto 0); + cout: out std_logic +); +end adder4; + +architecture struct of adder4 is + +signal y: std_logic_vector(4 downto 0); + +begin + y(0) <= cin; + cout <= y(4); + u: for i in 0 to 3 generate + p: entity work.fa(dataflow) port map (a(i), b(i), cin, s(i), cout => y(i+1)); + end generate; +end struct; diff --git a/vhdl-digital-design/ex1/adder4_tb.vhd b/vhdl-digital-design/ex1/adder4_tb.vhd @@ -0,0 +1,67 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity adder4_tb is +end adder4_tb; + +architecture behav of adder4_tb is + +signal a1, b1: std_logic_vector(3 downto 0); +signal cin1: std_logic; +signal s1: std_logic_vector(3 downto 0); +signal cout1: std_logic; + +component adder4 is port ( + a, b: in std_logic_vector(3 downto 0); + cin: in std_logic; + s: out std_logic_vector(3 downto 0); + cout: out std_logic +); +end component; + +begin + uut: adder4 port map ( + a => a1, + b => b1, + cin => cin1, + s => s1, + cout => cout1 + ); + + process begin + a1 <= "0000"; + b1 <= "0000"; + cin1 <= '0'; + wait for 20 ps; + + a1 <= "1111"; + b1 <= "1111"; + cin1 <= '0'; + wait for 20 ps; + + a1 <= "1111"; + b1 <= "1111"; + cin1 <= '1'; + wait for 20 ps; + + -- 3 + 5 (overflow) + a1 <= "0011"; + b1 <= "0101"; + cin1 <= '0'; + wait for 20 ps; + + -- -2 + 3 + -- 2 -> 0010 -> (2's complement) -> ~0010 | 0001 -> + -- 1101 | 0001 -> 1101 (+ cin) + a1 <= not "0010" or "0001"; + b1 <= "0011"; + cin1 <= '1'; + wait for 20 ps; + + -- -8 + 7 (~1000 | 0001 + cin) + a1 <= not "1000" or "0001"; + b1 <= "0111"; + cin1 <= '1'; + wait for 20 ps; + end process; +end behav; diff --git a/vhdl-digital-design/ex1/dec4to16.vhd b/vhdl-digital-design/ex1/dec4to16.vhd @@ -0,0 +1,28 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dec4to16 is port ( + a: in std_logic_vector(3 downto 0); + d: out std_logic_vector(15 downto 0) +); +end dec4to16; + +architecture dataflow of dec4to16 is +begin + d(0) <= not a(3) and not a(2) and not a(1) and not a(0); + d(1) <= not a(3) and not a(2) and not a(1) and a(0); + d(2) <= not a(3) and not a(2) and a(1) and not a(0); + d(3) <= not a(3) and not a(2) and a(1) and a(0); + d(4) <= not a(3) and a(2) and not a(1) and not a(0); + d(5) <= not a(3) and a(2) and not a(1) and a(0); + d(6) <= not a(3) and a(2) and a(1) and not a(0); + d(7) <= not a(3) and a(2) and a(1) and a(0); + d(8) <= a(3) and not a(2) and not a(1) and not a(0); + d(9) <= a(3) and not a(2) and not a(1) and a(0); + d(10) <= a(3) and not a(2) and a(1) and not a(0); + d(11) <= a(3) and not a(2) and a(1) and a(0); + d(12) <= a(3) and a(2) and not a(1) and not a(0); + d(13) <= a(3) and a(2) and not a(1) and a(0); + d(14) <= a(3) and a(2) and a(1) and not a(0); + d(15) <= a(3) and a(2) and a(1) and a(0); +end dataflow; diff --git a/vhdl-digital-design/ex1/dec4to16_tb.vhd b/vhdl-digital-design/ex1/dec4to16_tb.vhd @@ -0,0 +1,73 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dec4to16_tb is +end dec4to16_tb; + +architecture behav of dec4to16_tb is + +signal a1: std_logic_vector(3 downto 0); +signal d1: std_logic_vector(15 downto 0); + +component dec4to16 is port ( + a: in std_logic_vector(3 downto 0); + d: out std_logic_vector(15 downto 0) +); +end component; + +begin + uut: dec4to16 port map ( + a => a1, + d => d1 + ); + + process begin + a1 <= "0000"; + wait for 20 ps; + + a1 <= "0001"; + wait for 20 ps; + + a1 <= "0010"; + wait for 20 ps; + + a1 <= "0011"; + wait for 20 ps; + + a1 <= "0100"; + wait for 20 ps; + + a1 <= "0101"; + wait for 20 ps; + + a1 <= "0110"; + wait for 20 ps; + + a1 <= "0111"; + wait for 20 ps; + + a1 <= "1000"; + wait for 20 ps; + + a1 <= "1001"; + wait for 20 ps; + + a1 <= "1010"; + wait for 20 ps; + + a1 <= "1011"; + wait for 20 ps; + + a1 <= "1100"; + wait for 20 ps; + + a1 <= "1101"; + wait for 20 ps; + + a1 <= "1110"; + wait for 20 ps; + + a1 <= "1111"; + wait for 20 ps; + end process; +end behav; diff --git a/vhdl-digital-design/ex1/ex1.pdf b/vhdl-digital-design/ex1/ex1.pdf Binary files differ. diff --git a/vhdl-digital-design/ex1/fa.vhd b/vhdl-digital-design/ex1/fa.vhd @@ -2,8 +2,8 @@ library ieee; use ieee.std_logic_1164.all; entity fa is port ( - a, b, cin: in bit; - s, cout: out bit + a, b, cin: in std_logic; + s, cout: out std_logic ); end fa; diff --git a/vhdl-digital-design/ex1/fa_tb.vhd b/vhdl-digital-design/ex1/fa_tb.vhd @@ -6,12 +6,12 @@ end fa_tb; architecture behav of fa_tb is -signal a1, b1, cin1: bit; -signal s1, cout1: bit; +signal a1, b1, cin1: std_logic; +signal s1, cout1: std_logic; component fa is port ( - a, b, cin: in bit; - s, cout: out bit + a, b, cin: in std_logic; + s, cout: out std_logic ); end component; diff --git a/vhdl-digital-design/mux2to1.vhd b/vhdl-digital-design/ex1/mux2to1.vhd diff --git a/vhdl-digital-design/mux2to1_tb.vhd b/vhdl-digital-design/ex1/mux2to1_tb.vhd diff --git a/vhdl-digital-design/ex2/Makefile b/vhdl-digital-design/ex2/Makefile @@ -0,0 +1 @@ +include ../Makefile diff --git a/vhdl-digital-design/ex2/ff.vhd b/vhdl-digital-design/ex2/ff.vhd @@ -0,0 +1,15 @@ +entity ff is port ( + d: in bit; + clk: in bit; + q: out bit +); +end ff; + +architecture behav of ff is +begin + process (clk) begin + if (clk 'event and clk = '1') then + q <= d; + end if; + end process; +end behav; diff --git a/vhdl-digital-design/ex2/ff_tb.vhd b/vhdl-digital-design/ex2/ff_tb.vhd @@ -0,0 +1,63 @@ +entity ff_tb is +end ff_tb; + +architecture behav of ff_tb is + +signal d1: bit; +signal clk1: bit; +signal q1: bit; + +component ff is port ( + d: in bit; + clk: in bit; + q: out bit +); +end component; + +begin + uut: ff port map ( + d => d1, + clk => clk1, + q => q1 + ); + + process begin + clk1 <= '1'; + wait for 150 ns; + + clk1 <= '0'; + wait for 250 ns; + + clk1 <= '1'; + wait for 150 ns; + + clk1 <= '0'; + wait for 250 ns; + + clk1 <= '1'; + wait for 150 ns; + + clk1 <= '0'; + wait for 250 ns; + end process; + + process begin + d1 <= '1'; + wait for 280 ns; + + d1 <= '0'; + wait for 300 ns; + + d1 <= '1'; + wait for 250 ns; + + d1 <= '0'; + wait for 150 ns; + + d1 <= '1'; + wait for 75 ns; + + d1 <= '0'; + wait for 150 ns; + end process; +end behav; diff --git a/vhdl-digital-design/ex2/ffrst.vhd b/vhdl-digital-design/ex2/ffrst.vhd @@ -0,0 +1,18 @@ +entity ffrst is port ( + d: in bit; + clk: in bit; + rst: in bit; + q: out bit +); +end ffrst; + +architecture behav of ffrst is +begin + process (clk, rst) begin + if (rst = '0') then + q <= '0'; + elsif (clk 'event and clk = '1') then + q <= d; + end if; + end process; +end behav; diff --git a/vhdl-digital-design/ex2/latch.vhd b/vhdl-digital-design/ex2/latch.vhd @@ -0,0 +1,15 @@ +entity latch is port ( + d: in bit; + en: in bit; + q: out bit +); +end latch; + +architecture behav of latch is +begin + process (d, en) begin + if (en = '1') then + q <= d; + end if; + end process; +end behav; diff --git a/vhdl-digital-design/ex2/latch_tb.vhd b/vhdl-digital-design/ex2/latch_tb.vhd @@ -0,0 +1,63 @@ +entity latch_tb is +end latch_tb; + +architecture behav of latch_tb is + +signal d1: bit; +signal en1: bit; +signal q1: bit; + +component latch is port ( + d: in bit; + en: in bit; + q: out bit +); +end component; + +begin + uut: latch port map ( + d => d1, + en => en1, + q => q1 + ); + + process begin + en1 <= '1'; + wait for 150 ns; + + en1 <= '0'; + wait for 250 ns; + + en1 <= '1'; + wait for 150 ns; + + en1 <= '0'; + wait for 250 ns; + + en1 <= '1'; + wait for 150 ns; + + en1 <= '0'; + wait for 250 ns; + end process; + + process begin + d1 <= '1'; + wait for 280 ns; + + d1 <= '0'; + wait for 300 ns; + + d1 <= '1'; + wait for 250 ns; + + d1 <= '0'; + wait for 150 ns; + + d1 <= '1'; + wait for 75 ns; + + d1 <= '0'; + wait for 150 ns; + end process; +end behav;
