commit 85632e5712602f0d11099a408b4327bed9bc09e0
parent f598344ca4bda3170af95e5d88f3d7381d1c2227
Author: Christos Margiolis <christos@margiolis.net>
Date: Mon, 26 Apr 2021 16:17:44 +0300
L
Diffstat:
16 files changed, 347 insertions(+), 116 deletions(-)
diff --git a/c-os2/ex2/ex1_1.c b/c-os2/ex2/ex1_1.c
@@ -84,7 +84,8 @@ main(int argc, char *argv[])
while (n--) {
for (i = 0; i < len; i++) {
/* Get appropriate string. */
- f->str = strdup(nums[i % len]);
+ if ((f->str = strdup(nums[i % len])) == NULL)
+ die("strdup");
if (pthread_create(&tds[i], NULL, tdprint, (void *)f) != 0)
die("pthread_create");
if (pthread_join(tds[i], NULL) != 0)
diff --git a/java-development/Prime.java b/java-development/Prime.java
@@ -0,0 +1,36 @@
+import java.io.*;
+
+class Prime {
+ public static void main(String[] args) {
+ try {
+ FileOutputStream fos = new FileOutputStream(args[0]);
+ BufferedOutputStream bos = new BufferedOutputStream(fos);
+ DataOutputStream dos = new DataOutputStream(bos);
+ int i = 0;
+ int n = 2;
+
+ while (i < 100) {
+ if (is_prime(n)) {
+ dos.writeInt(n);
+ i++;
+ }
+ n++;
+ }
+ dos.close();
+ fos.close();
+ } catch (FileNotFoundException e) {
+ System.err.println("File not found");
+ return;
+ } catch (IOException e) {
+ System.err.println("IO Exception");
+ return;
+ }
+ }
+
+ private static boolean is_prime(int n) {
+ for (int i = 2; i < n; i++)
+ if (n % i == 0)
+ return false;
+ return true;
+ }
+}
diff --git a/java-development/csv/Album.java b/java-development/csv/Album.java
@@ -0,0 +1,36 @@
+class Album {
+ private String title;
+ private String artist;
+ private Integer year;
+ private Float price;
+
+ Album(String title, String artist, Integer year, Float price) {
+ this.title = title;
+ this.artist = artist;
+ this.year = year;
+ this.price = price;
+ }
+
+ public String get_title() {
+ return title;
+ }
+
+ public String get_artist() {
+ return artist;
+ }
+
+ public Integer get_year() {
+ return year;
+ }
+
+ public Float get_price() {
+ return price;
+ }
+
+ @Override
+ public String toString () {
+ return String.format("%-40s\t", title) +
+ String.format("%-30s\t", artist) +
+ year + "\t" + price;
+ }
+}
diff --git a/java-development/csv/Main.java b/java-development/csv/Main.java
@@ -3,10 +3,10 @@ import java.util.ArrayList;
class Main {
public static void main(String[] args) {
- ArrayList<Movie> movies = new ArrayList<Movie>();
+ ArrayList<Album> albums = new ArrayList<Album>();
BufferedReader br;
File f;
- String fields[] = new String[3];
+ String fields[];
String str;
String sortby;
@@ -16,32 +16,35 @@ class Main {
br = new BufferedReader(new FileReader(f));
while ((str = br.readLine()) != null) {
- fields = str.split("\\|");
- movies.add(new Movie(fields[0],
- Integer.parseInt(fields[1]),
- Float.parseFloat(fields[2])));
+ fields = str.split("\\;");
+ albums.add(new Album(fields[0], fields[1],
+ Integer.parseInt(fields[2]),
+ Float.parseFloat(fields[3])));
}
br.close();
} catch (FileNotFoundException e) {
- System.err.println("file not found");
+ System.err.println("No such file");
return;
} catch (IOException e) {
- System.err.println("IO Excetion");
+ System.err.println("IO Exception");
return;
} catch (ArrayIndexOutOfBoundsException e) {
- System.err.println("usage: java Main sortby file\n");
- System.err.println("You can sort by:\n\ttitle\n\tyear\n\tprice");
+ System.err.println("Usage: java Main sortby file\n");
+ System.err.println("You can sort by:\n\ttitle\n\t" +
+ "artist\n\tyear\n\tprice");
return;
}
if (sortby.equals("title"))
- movies.sort((o1, o2) -> o1.get_title().compareTo(o2.get_title()));
+ albums.sort((o1, o2) -> o1.get_title().compareTo(o2.get_title()));
+ else if (sortby.equals("artist"))
+ albums.sort((o1, o2) -> o1.get_artist().compareTo(o2.get_artist()));
else if (sortby.equals("year"))
- movies.sort((o1, o2) -> o1.get_year().compareTo(o2.get_year()));
+ albums.sort((o1, o2) -> o1.get_year().compareTo(o2.get_year()));
else if (sortby.equals("price"))
- movies.sort((o1, o2) -> o1.get_price().compareTo(o2.get_price()));
+ albums.sort((o1, o2) -> o1.get_price().compareTo(o2.get_price()));
- for (Movie m : movies)
+ for (Album m : albums)
System.out.println(m);
}
}
diff --git a/java-development/csv/Movie.java b/java-development/csv/Movie.java
@@ -1,28 +0,0 @@
-class Movie {
- private String title;
- private Integer year;
- private Float price;
-
- Movie(String title, Integer year, Float price) {
- this.title = title;
- this.year = year;
- this.price = price;
- }
-
- public String get_title() {
- return title;
- }
-
- public Integer get_year() {
- return year;
- }
-
- public Float get_price() {
- return price;
- }
-
- @Override
- public String toString () {
- return String.format("%-20s\t", title) + year + "\t" + price;
- }
-}
diff --git a/java-development/csv/data b/java-development/csv/data
@@ -0,0 +1,10 @@
+The Dark Side Of The Moon;Pink Floyd;1973;27.50
+In Rock;Deep Purple;1970;25.20
+Back In Black;AC/DC;1980;27.00
+Led Zeppelin IV;Led Zeppelin;1971;22.25
+Rumours;Fleetwood Mac;1977;23.40
+Paranoid;Black Sabbath;1970;24.90
+Sgt. Pepper's Lonely Hearts Club Band;The Beatles;1966;26.50
+Sticky Fingers;The Rolling Stones;1971;29.90
+The Magician's Birthday;Uriah Heep;1972;29.90
+Appetite For Destruction;Guns N' Roses;1987;30.50
diff --git a/octave-signals-systems/ex3/doc.pdf b/octave-signals-systems/ex3/doc.pdf
Binary files differ.
diff --git a/octave-signals-systems/ex3/doc.tex b/octave-signals-systems/ex3/doc.tex
@@ -1,73 +0,0 @@
-\documentclass{article}
-\usepackage[utf8]{inputenc}
-\usepackage[greek,english]{babel} \usepackage{alphabeta}
-\usepackage{fancyhdr}
-\usepackage{listings}
-\usepackage{mathtools}
-\usepackage{xcolor}
-\usepackage{graphicx}
-\usepackage{float}
-\usepackage[backend=biber]{biblatex}
-
-\title{Σήματα και Συστήματα - Εργασία 3}
-\author{Χρήστος Μαργιώλης - 19390133}
-\date{Απρίλιος 2021}
-
-\begin{document}
-
-\begin{titlepage}
- \maketitle
- \begin{figure}[t!]
- \begin{center}
- \includegraphics[scale=0.3]{./res/uniwalogo.png} \\
- \Large
- \textbf{Πανεπιστήμιο Δυτικής Αττικής} \\
- \large
- Τμήμα Μηχανικών Πληροφορικής και Ηλεκτρονικών Υπολογιστών
- \end{center}
- \end{figure}
-\end{titlepage}
-
-\renewcommand{\contentsname}{Περιεχόμενα}
-\tableofcontents
-
-\section{'Ασκηση 1}
-
-\begin{itemize}
- \item 'Εστω το σύστημα ολοκληρωτή που φαίνεται στο παρκάτω
- σχήμα (φυλλάδιο άσκηση σελίδα 12). 'Ενα τέτοιο
- σύστημα δέχεται ως είσοδο ένα σήμα $x(t)$ και η έξοδος
- $y(t)$ δίνεται από την σχέση:
- \[y(t) = \int_{-\infty}^{t} x(τ)dτ\]
- Σας ζητείται να μελετήσετε αυτό το σύστημα και να
- απαντήσετε ως προς τις ιδιότητες:
- \begin{itemize}
- \item Γραμμικό ή μη γραμμικό.
- \item Δυναμικό ή στατικό.
- \item Αιτιατό ή μη αιτιατό.
- \item Χρονικά αμετάβλητο ή χρονικά μεταβαλλόμενο.
- \item Ευσταθές ή ασταθές.
- \end{itemize}
-\end{itemize}
-
-<++>
-
-\section{'Ασκηση 2}
-
-\begin{itemize}
- \item Να εξετάσετε ως προς την ευστάθεια το σύστημα με σχέση
- εισόδου-εξόδου $y(t) = e^{x(t)}$.
-\end{itemize}
-
-<++>
-
-\section{'Ασκηση 3}
-
-\begin{itemize}
- \item Να εξεταστεί εάν το σύστημα που διέπεται από την σχέση
- εισόδου-εξόδου $y(t) = x(t/4)$ είναι αιτιατό.
-\end{itemize}
-
-<++>
-
-\end{document}
diff --git a/octave-signals-systems/ex3/res/uniwalogo.png b/octave-signals-systems/ex3/res/uniwalogo.png
Binary files differ.
diff --git a/vhdl-digital-design/ex2/reg.vhd b/vhdl-digital-design/ex2/reg.vhd
@@ -0,0 +1,22 @@
+entity reg is port (
+ d: in bit_vector(3 downto 0);
+ clk: in bit;
+ clr: in bit;
+ q: out bit_vector(3 downto 0)
+);
+end reg;
+
+architecture struct of reg is
+component ffrst is port (
+ d: in bit;
+ clk: in bit;
+ rst: in bit;
+ q: out bit
+);
+end component;
+
+begin
+ u: for i in 0 to 3 generate
+ f: ffrst port map (d(i), clk, clr, q(i));
+ end generate;
+end struct;
diff --git a/vhdl-digital-design/ex2/reg_tb.vhd b/vhdl-digital-design/ex2/reg_tb.vhd
@@ -0,0 +1,48 @@
+entity reg_tb is
+end reg_tb;
+
+architecture behav of reg_tb is
+
+signal d1: bit_vector(3 downto 0);
+signal clk1: bit;
+signal clr1: bit;
+signal q1: bit_vector(3 downto 0);
+
+component reg is port (
+ d: in bit_vector(3 downto 0);
+ clk: in bit;
+ clr: in bit;
+ q: out bit_vector(3 downto 0)
+);
+end component;
+
+begin
+ uut: reg port map (
+ d => d1,
+ clk => clk1,
+ clr => clr1,
+ q => q1
+ );
+
+ process begin
+ clr1 <= '0';
+ clk1 <= '0';
+ d1 <= "0001";
+ wait for 250 ns;
+
+ clr1 <= '1';
+ clk1 <= '1';
+ d1 <= "0001";
+ wait for 250 ns;
+
+ clr1 <= '1';
+ clk1 <= '0';
+ d1 <= "0011";
+ wait for 250 ns;
+
+ clr1 <= '1';
+ clk1 <= '1';
+ d1 <= "0101";
+ wait for 250 ns;
+ end process;
+end behav;+
\ No newline at end of file
diff --git a/vhdl-digital-design/ex2/shift4.vhd b/vhdl-digital-design/ex2/shift4.vhd
@@ -0,0 +1,32 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity shift4 is port (
+ d: in std_logic_vector(3 downto 0);
+ en: in std_logic;
+ load: in std_logic;
+ sin: in std_logic;
+ clk: in std_logic;
+ q: out std_logic_vector(3 downto 0)
+);
+end shift4;
+
+architecture behav of shift4 is
+
+signal qq: std_logic_vector(3 downto 0);
+
+begin
+ process (clk) begin
+ if (rising_edge(clk)) then
+ if (load = '1') then
+ q <= d;
+ elsif (en = '1') then
+ qq(0) <= qq(1);
+ qq(1) <= qq(2);
+ qq(2) <= qq(3);
+ qq(3) <= sin;
+ end if;
+ end if;
+ end process;
+ q <= qq;
+end behav;
diff --git a/vhdl-digital-design/ex2/shift4_tb.vhd b/vhdl-digital-design/ex2/shift4_tb.vhd
@@ -0,0 +1,51 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity shift4_tb is
+end shift4_tb;
+
+architecture behav of shift4_tb is
+
+signal d1: std_logic_vector(3 downto 0);
+signal en1: std_logic;
+signal load1: std_logic;
+signal sin1: std_logic;
+signal clk1: std_logic;
+signal q1: std_logic_vector(3 downto 0);
+
+component shift4 is port (
+ d: in std_logic_vector(3 downto 0);
+ en: in std_logic;
+ load: in std_logic;
+ sin: in std_logic;
+ clk: in std_logic;
+ q: out std_logic_vector(3 downto 0)
+);
+end component;
+
+begin
+ uut: shift4 port map (
+ d => d1,
+ en => en1,
+ load => load1,
+ sin => sin1,
+ clk => clk1,
+ q => q1
+ );
+
+ process begin
+ d1 <= "1011";
+ load1 <= '1';
+ en1 <= '0';
+ sin1 <= '1';
+ clk1 <= '1';
+ wait for 250 ns;
+
+ d1 <= "1011";
+ load1 <= '0';
+ en1 <= '1';
+ sin1 <= '0';
+ clk1 <= '1';
+ wait for 250 ns;
+ end process;
+end behav;
diff --git a/vhdl-digital-design/ex2/shiftn.vhd b/vhdl-digital-design/ex2/shiftn.vhd
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity shiftn is
+ generic (n: integer := 8);
+ port (
+ d: in std_logic_vector(n - 1 downto 0);
+ en: in std_logic;
+ load: in std_logic;
+ sin: in std_logic;
+ clk: in std_logic;
+ q: out std_logic_vector(n - 1 downto 0)
+);
+end shiftn;
+
+architecture behav of shiftn is
+
+signal qq: std_logic_vector(n - 1 downto 0);
+
+begin
+ process (clk) begin
+ if (rising_edge(clk)) then
+ if (load = '1') then
+ q <= d;
+ elsif (en = '1') then
+ u: for i in 0 to n - 2 loop
+ qq(i) <= qq(i + 1);
+ end loop;
+ qq(n - 1) <= sin;
+ end if;
+ end if;
+ end process;
+ q <= qq;
+end behav;+
\ No newline at end of file
diff --git a/vhdl-digital-design/ex2/upcount.vhd b/vhdl-digital-design/ex2/upcount.vhd
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity upcount is port (
+ clk: in std_logic;
+ rst: in std_logic;
+ q: inout std_logic_vector(1 downto 0)
+);
+end upcount;
+
+architecture behav of upcount is
+begin
+ process (clk, rst) begin
+ if (rst = '1') then
+ q <= "00";
+ elsif (rising_edge(clk)) then
+ q <= q + 1;
+ end if;
+ end process;
+end behav;
diff --git a/vhdl-digital-design/ex2/upcount_tb.vhd b/vhdl-digital-design/ex2/upcount_tb.vhd
@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity upcount_tb is
+end upcount_tb;
+
+architecture behav of upcount_tb is
+
+signal clk1: std_logic := '1';
+signal rst1: std_logic := '1';
+signal q1: std_logic_vector(1 downto 0);
+
+component upcount is port (
+ clk: in std_logic;
+ rst: in std_logic;
+ q: inout std_logic_vector(1 downto 0)
+);
+end component;
+
+begin
+ uut: upcount port map (
+ clk => clk1,
+ rst => rst1,
+ q => q1
+ );
+
+ process begin
+ rst1 <= '0';
+ clk1 <= '0';
+ wait for 250 ns;
+
+ clk1 <= '1';
+ wait for 250 ns;
+ end process;
+end behav;
