commit bd3fdb78daf038d3a1f6ac1d7c4aad09e19bb795 parent 689708e31e84dcc493b7a38d2f1a01412ebcf210 Author: Christos Margiolis <christos@margiolis.net> Date: Sun, 18 Jul 2021 20:51:15 +0300 mips done, finally... Diffstat:
48 files changed, 303 insertions(+), 282 deletions(-)
diff --git a/vhdl_digital_design/project/part0_mux_dec/Makefile b/vhdl_digital_design/project/part1_mux_dec/Makefile diff --git a/vhdl_digital_design/project/part0_mux_dec/dec2to4.vhd b/vhdl_digital_design/project/part1_mux_dec/dec2to4.vhd diff --git a/vhdl_digital_design/project/part0_mux_dec/mux2to1.vhd b/vhdl_digital_design/project/part1_mux_dec/mux2to1.vhd diff --git a/vhdl_digital_design/project/part0_mux_dec/mux2to1gen.vhd b/vhdl_digital_design/project/part1_mux_dec/mux2to1gen.vhd diff --git a/vhdl_digital_design/project/part0_mux_dec/mux2to1gen_tb.vhd b/vhdl_digital_design/project/part1_mux_dec/mux2to1gen_tb.vhd diff --git a/vhdl_digital_design/project/part1_alu/Makefile b/vhdl_digital_design/project/part2_alu/Makefile diff --git a/vhdl_digital_design/project/part1_alu/alu.vhd b/vhdl_digital_design/project/part2_alu/alu.vhd diff --git a/vhdl_digital_design/project/part1_alu/alu_tb.vhd b/vhdl_digital_design/project/part2_alu/alu_tb.vhd diff --git a/vhdl_digital_design/project/part2_alu_ctrl/Makefile b/vhdl_digital_design/project/part3_alu_ctrl/Makefile diff --git a/vhdl_digital_design/project/part2_alu_ctrl/alu.vhd b/vhdl_digital_design/project/part3_alu_ctrl/alu.vhd diff --git a/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl.vhd b/vhdl_digital_design/project/part3_alu_ctrl/alu_ctrl.vhd diff --git a/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl_tb.vhd b/vhdl_digital_design/project/part3_alu_ctrl/alu_ctrl_tb.vhd diff --git a/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl_test_alu.vhd b/vhdl_digital_design/project/part3_alu_ctrl/alu_ctrl_test_alu.vhd diff --git a/vhdl_digital_design/project/part2_alu_ctrl/alu_ctrl_test_alu_tb.vhd b/vhdl_digital_design/project/part3_alu_ctrl/alu_ctrl_test_alu_tb.vhd diff --git a/vhdl_digital_design/project/part3_ctrl_signext_lshift/Makefile b/vhdl_digital_design/project/part4_ctrl_signext_lshift/Makefile diff --git a/vhdl_digital_design/project/part3_ctrl_signext_lshift/ctrl.vhd b/vhdl_digital_design/project/part4_ctrl_signext_lshift/ctrl.vhd diff --git a/vhdl_digital_design/project/part3_ctrl_signext_lshift/ctrl_tb.vhd b/vhdl_digital_design/project/part4_ctrl_signext_lshift/ctrl_tb.vhd diff --git a/vhdl_digital_design/project/part3_ctrl_signext_lshift/shl2.vhd b/vhdl_digital_design/project/part4_ctrl_signext_lshift/shl2.vhd diff --git a/vhdl_digital_design/project/part3_ctrl_signext_lshift/shl2_tb.vhd b/vhdl_digital_design/project/part4_ctrl_signext_lshift/shl2_tb.vhd diff --git a/vhdl_digital_design/project/part3_ctrl_signext_lshift/sign_ext.vhd b/vhdl_digital_design/project/part4_ctrl_signext_lshift/sign_ext.vhd diff --git a/vhdl_digital_design/project/part3_ctrl_signext_lshift/sign_ext_tb.vhd b/vhdl_digital_design/project/part4_ctrl_signext_lshift/sign_ext_tb.vhd diff --git a/vhdl_digital_design/project/part4_instrmem_datamem/Makefile b/vhdl_digital_design/project/part5_instrmem_datamem/Makefile diff --git a/vhdl_digital_design/project/part4_instrmem_datamem/datamem.vhd b/vhdl_digital_design/project/part5_instrmem_datamem/datamem.vhd diff --git a/vhdl_digital_design/project/part4_instrmem_datamem/datamem_tb.vhd b/vhdl_digital_design/project/part5_instrmem_datamem/datamem_tb.vhd diff --git a/vhdl_digital_design/project/part4_instrmem_datamem/instrmem.vhd b/vhdl_digital_design/project/part5_instrmem_datamem/instrmem.vhd diff --git a/vhdl_digital_design/project/part4_instrmem_datamem/instrmem_tb.vhd b/vhdl_digital_design/project/part5_instrmem_datamem/instrmem_tb.vhd diff --git a/vhdl_digital_design/project/part6_mips_r_ops/adder32.vhd b/vhdl_digital_design/project/part6_mips_r_ops/adder32.vhd @@ -1,32 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity adder32 is port ( - a: in std_logic_vector(31 downto 0); - b: in std_logic_vector(31 downto 0); - cin: in std_logic; - s: out std_logic_vector(31 downto 0); - cout: out std_logic -); -end adder32; - -architecture struct of adder32 is - -component fa is port ( - a: in std_logic; - b: in std_logic; - cin: in std_logic; - s: out std_logic; - cout: out std_logic -); -end component; - -signal y: std_logic_vector(32 downto 0); - -begin - y(0) <= cin; - cout <= y(32); - adder_gen: for i in 0 to 31 generate - adder_map: fa port map (a(i), b(i), cin, s(i), cout => y(i+1)); - end generate; -end struct; diff --git a/vhdl_digital_design/project/part6_mips_r_ops/fa.vhd b/vhdl_digital_design/project/part6_mips_r_ops/fa.vhd @@ -1,17 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity fa is port ( - a: in std_logic; - b: in std_logic; - cin: in std_logic; - s: out std_logic; - cout: out std_logic -); -end fa; - -architecture dataflow of fa is -begin - s <= a xor b xor cin; - cout <= (a and b) or (cin and (a xor b)); -end dataflow; diff --git a/vhdl_digital_design/project/part6_mips_r_ops/instrmem.vhd b/vhdl_digital_design/project/part6_mips_r_ops/instrmem.vhd @@ -1,36 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.numeric_std.all; - -entity instrmem is port ( - addr: in std_logic_vector(3 downto 0); - c: out std_logic_vector(31 downto 0) -); -end instrmem; - -architecture dataflow of instrmem is - -type instr_arr is array(0 to 15) of std_logic_vector (31 downto 0); -constant instr_mem: instr_arr := ( - "00000000000000000000000000000000", -- 0 - "00000000000000000000000000000000", -- 1 - "00000000000000000000000000000000", -- 2 - "00000000000000000000000000000000", -- 3 - "00000000000000000000000000000000", -- 4 - "00000000000000000000000000000000", -- 5 - "00000000000000000000000000000000", -- 6 - "00000000000000000000000000000000", -- 7 - "00000000000000000000000000000000", -- 8 - "00000000000000000000000000000000", -- 9 - "00000000000000000000000000000000", -- 10 - "00000000000000000000000000000000", -- 11 - "00000000000000000000000000000000", -- 12 - "00000000000000000000000000000000", -- 13 - "00000000000000000000000000000000", -- 14 - "00000000000000000000000000000000" -- 15 -); - -begin - c <= instr_mem(to_integer(unsigned(addr))); -end dataflow; diff --git a/vhdl_digital_design/project/part6_mips_r_ops/mips.vhd b/vhdl_digital_design/project/part6_mips_r_ops/mips.vhd @@ -1,176 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity mips is port ( - m_clk: in std_logic; - m_rst: in std_logic; - m_instr: out std_logic_vector(31 downto 0); - m_raddr1: out std_logic_vector(4 downto 0); - m_raddr2: out std_logic_vector(4 downto 0); - m_waddr: out std_logic_vector(4 downto 0); - m_reg1: out std_logic_vector(31 downto 0); - m_reg2: out std_logic_vector(31 downto 0); - m_out: out std_logic_vector(31 downto 0) -); -end mips; - -architecture struct of mips is - -component alu is -generic ( - sz: natural := 32 -); -port ( - alu_in1: in std_logic_vector(sz-1 downto 0); - alu_in2: in std_logic_vector(sz-1 downto 0); - alu_ctrl: in std_logic_vector(3 downto 0); - alu_out: out std_logic_vector(sz-1 downto 0); - alu_zero: out std_logic -); -end component; - -component regfile_ext is -generic ( - sz: natural := 32; - addrw: natural := 5 -); -port ( - idata: in std_logic_vector(sz-1 downto 0); - raddr1: in std_logic_vector(addrw-1 downto 0); - raddr2: in std_logic_vector(addrw-1 downto 0); - waddr: in std_logic_vector(addrw-1 downto 0); - we: in std_logic; - clk: in std_logic; - rst: in std_logic; - odata1: out std_logic_vector(sz-1 downto 0); - odata2: out std_logic_vector(sz-1 downto 0) -); -end component; - -component instrmem is port ( - addr: in std_logic_vector(3 downto 0); - c: out std_logic_vector(31 downto 0) -); -end component; - -component ctrl is port ( - funct: in std_logic_vector(5 downto 0); - reg_dst: out std_logic; - reg_wr: out std_logic; - alu_src: out std_logic; - branch: out std_logic; - mem_rd: out std_logic; - mem_wr: out std_logic; - mem_toreg: out std_logic; - alu_op: out std_logic_vector(1 downto 0) -); -end component; - -component alu_ctrl is port ( - funct: in std_logic_vector(5 downto 0); - alu_op: in std_logic_vector(1 downto 0); - op: out std_logic_vector(3 downto 0) -); -end component; - -component pc is port ( - clk: in std_logic; - rst: in std_logic; - ipc: in std_logic_vector(3 downto 0); - opc: out std_logic_vector(3 downto 0) -); -end component; - -component adder32 is port ( - a: in std_logic_vector(31 downto 0); - b: in std_logic_vector(31 downto 0); - cin: in std_logic; - s: out std_logic_vector(31 downto 0); - cout: out std_logic -); -end component; - -signal s_instr: std_logic_vector(31 downto 0); -signal s_op: std_logic_vector(3 downto 0); -signal s_alu_out: std_logic_vector(31 downto 0); -signal s_alu_zero: std_logic; -signal s_reg_out1: std_logic_vector(31 downto 0); -signal s_reg_out2: std_logic_vector(31 downto 0); -signal s_reg_wr: std_logic; -signal s_reg_dst: std_logic; -signal s_alu_src: std_logic; -signal s_branch: std_logic; -signal s_mem_rd: std_logic; -signal s_mem_wr: std_logic; -signal s_mem_toreg: std_logic; -signal s_alu_op: std_logic_vector(1 downto 0); -signal s_opc: std_logic_vector(3 downto 0); -signal s_adder_to_pc: std_logic_vector(3 downto 0); -constant c_pc_add_val: std_logic_vector(3 downto 0) := "0100"; - -begin - alu_map: alu port map ( - alu_in1 => s_reg_out1, - alu_in2 => s_reg_out2, - alu_ctrl => s_op, - alu_out => s_alu_out, - alu_zero => s_alu_zero - ); - - regfile_ext_map: regfile_ext port map ( - idata => s_alu_out, - raddr1 => s_instr(25 downto 21), - raddr2 => s_instr(20 downto 16), - waddr => s_instr(15 downto 11), - we => s_reg_wr, - clk => m_clk, - rst => m_rst, - odata1 => s_reg_out1, - odata2 => s_reg_out2 - ); - - instrmem_map: instrmem port map ( - addr => s_opc, - c => s_instr - ); - - ctrl_map: ctrl port map ( - funct => s_instr(31 downto 26), - reg_dst => s_reg_dst, - reg_wr => s_reg_wr, - alu_src => s_alu_src, - branch => s_branch, - mem_rd => s_mem_rd, - mem_wr => s_mem_wr, - mem_toreg => s_mem_toreg, - alu_op => s_alu_op - ); - - alu_ctrl_map: alu_ctrl port map ( - funct => s_instr(5 downto 0), - alu_op => s_alu_op, - op => s_op - ); - - - pc_map: pc port map ( - clk => m_clk, - rst => m_rst, - ipc => s_adder_to_pc, - opc => s_opc - ); - - adder32_map: adder32 port map ( - a => s_opc, - b => c_pc_add_val - oval => s_adder_to_pc - ); - - m_instr <= s_instr; - m_raddr1 <= s_instr(25 downto 21); - m_raddr2 <= s_instr(20 downto 16); - m_waddr <= s_instr(15 downto 11); - m_reg1 <= s_reg_out1; - m_reg2 <= s_reg_out2; - m_out <= s_alu_out; -end struct; diff --git a/vhdl_digital_design/project/part6_mips_r_ops/pc.vhd b/vhdl_digital_design/project/part6_mips_r_ops/pc.vhd @@ -1,21 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity pc is port ( - clk: in std_logic; - rst: in std_logic; - ipc: in std_logic_vector(3 downto 0); - opc: out std_logic_vector(3 downto 0) -); -end pc; - -architecture behav of pc is -begin - process (clk) begin - if (rst = '1') then - opc <= "0000"; - elsif (rising_edge(clk)) then - opc <= ipc; - end if; - end process; -end behav; diff --git a/vhdl_digital_design/project/part5_regfile/Makefile b/vhdl_digital_design/project/part6_regfile/Makefile diff --git a/vhdl_digital_design/project/part5_regfile/reg.vhd b/vhdl_digital_design/project/part6_regfile/reg.vhd diff --git a/vhdl_digital_design/project/part5_regfile/reg_tb.vhd b/vhdl_digital_design/project/part6_regfile/reg_tb.vhd diff --git a/vhdl_digital_design/project/part5_regfile/regfile.vhd b/vhdl_digital_design/project/part6_regfile/regfile.vhd diff --git a/vhdl_digital_design/project/part5_regfile/regfile_ext.vhd b/vhdl_digital_design/project/part6_regfile/regfile_ext.vhd diff --git a/vhdl_digital_design/project/part5_regfile/regfile_ext_tb.vhd b/vhdl_digital_design/project/part6_regfile/regfile_ext_tb.vhd diff --git a/vhdl_digital_design/project/part5_regfile/regfile_tb.vhd b/vhdl_digital_design/project/part6_regfile/regfile_tb.vhd diff --git a/vhdl_digital_design/project/part6_mips_r_ops/Makefile b/vhdl_digital_design/project/part7_mips_r_ops/Makefile diff --git a/vhdl_digital_design/project/part7_mips_r_ops/adder32.vhd b/vhdl_digital_design/project/part7_mips_r_ops/adder32.vhd @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; + +entity adder32 is port ( + x: in std_logic_vector(31 downto 0); + y: in std_logic_vector(31 downto 0); + z: out std_logic_vector(31 downto 0) +); +end adder32; + +architecture dataflow of adder32 is +begin + z <= std_logic_vector(unsigned(x) + unsigned(y)); +end dataflow; diff --git a/vhdl_digital_design/project/part6_mips_r_ops/alu.vhd b/vhdl_digital_design/project/part7_mips_r_ops/alu.vhd diff --git a/vhdl_digital_design/project/part6_mips_r_ops/alu_ctrl.vhd b/vhdl_digital_design/project/part7_mips_r_ops/alu_ctrl.vhd diff --git a/vhdl_digital_design/project/part6_mips_r_ops/ctrl.vhd b/vhdl_digital_design/project/part7_mips_r_ops/ctrl.vhd diff --git a/vhdl_digital_design/project/part7_mips_r_ops/instrmem.vhd b/vhdl_digital_design/project/part7_mips_r_ops/instrmem.vhd @@ -0,0 +1,53 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity instrmem is port ( + addr: in std_logic_vector(31 downto 0); + c: out std_logic_vector(31 downto 0) +); +end instrmem; + +architecture dataflow of instrmem is + +type instr_arr is array(0 to 31) of std_logic_vector (31 downto 0); +constant instr_mem: instr_arr := ( + "00000000010001100010000000100000", -- 0 add $4, $2, $6 + "00000000010001100010100000100010", -- 1 sub $5, $2, $6 + "11111100100001010000000000000000", -- 2 read $4, $5 + "00000000000000000000000000000000", -- 3 + "00000000000000000000000000000000", -- 4 + "00000000000000000000000000000000", -- 5 + "00000000000000000000000000000000", -- 6 + "00000000000000000000000000000000", -- 7 + "00000000000000000000000000000000", -- 8 + "00000000000000000000000000000000", -- 9 + "00000000000000000000000000000000", -- 10 + "00000000000000000000000000000000", -- 11 + "00000000000000000000000000000000", -- 12 + "00000000000000000000000000000000", -- 13 + "00000000000000000000000000000000", -- 14 + "00000000000000000000000000000000", -- 15 + "00000000000000000000000000000000", -- 16 + "00000000000000000000000000000000", -- 17 + "00000000000000000000000000000000", -- 18 + "00000000000000000000000000000000", -- 19 + "00000000000000000000000000000000", -- 20 + "00000000000000000000000000000000", -- 21 + "00000000000000000000000000000000", -- 22 + "00000000000000000000000000000000", -- 23 + "00000000000000000000000000000000", -- 24 + "00000000000000000000000000000000", -- 25 + "00000000000000000000000000000000", -- 26 + "00000000000000000000000000000000", -- 27 + "00000000000000000000000000000000", -- 28 + "00000000000000000000000000000000", -- 29 + "00000000000000000000000000000000", -- 30 + "00000000000000000000000000000000" -- 31 +); + +begin + -- Our addresses are multiples of 4, so ignore the last 2 bits. + c <= instr_mem(to_integer(unsigned(addr(31 downto 2)))); +end dataflow; diff --git a/vhdl_digital_design/project/part7_mips_r_ops/mips.vhd b/vhdl_digital_design/project/part7_mips_r_ops/mips.vhd @@ -0,0 +1,158 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity mips is port ( + m_clk: in std_logic; + m_rst: in std_logic +); +end mips; + +architecture struct of mips is + +component alu is +generic ( + sz: natural := 32 +); +port ( + alu_in1: in std_logic_vector(sz-1 downto 0); + alu_in2: in std_logic_vector(sz-1 downto 0); + alu_ctrl: in std_logic_vector(3 downto 0); + alu_out: out std_logic_vector(sz-1 downto 0); + alu_zero: out std_logic +); +end component; + +component regfile_ext is +generic ( + sz: natural := 32; + addrw: natural := 5 +); +port ( + idata: in std_logic_vector(sz-1 downto 0); + raddr1: in std_logic_vector(addrw-1 downto 0); + raddr2: in std_logic_vector(addrw-1 downto 0); + waddr: in std_logic_vector(addrw-1 downto 0); + we: in std_logic; + clk: in std_logic; + rst: in std_logic; + odata1: out std_logic_vector(sz-1 downto 0); + odata2: out std_logic_vector(sz-1 downto 0) +); +end component; + +component instrmem is port ( + addr: in std_logic_vector(31 downto 0); + c: out std_logic_vector(31 downto 0) +); +end component; + +component ctrl is port ( + funct: in std_logic_vector(5 downto 0); + reg_dst: out std_logic; + reg_wr: out std_logic; + alu_src: out std_logic; + branch: out std_logic; + mem_rd: out std_logic; + mem_wr: out std_logic; + mem_toreg: out std_logic; + alu_op: out std_logic_vector(1 downto 0) +); +end component; + +component alu_ctrl is port ( + funct: in std_logic_vector(5 downto 0); + alu_op: in std_logic_vector(1 downto 0); + op: out std_logic_vector(3 downto 0) +); +end component; + +component adder32 is port ( + x: in std_logic_vector(31 downto 0); + y: in std_logic_vector(31 downto 0); + z: out std_logic_vector(31 downto 0) +); +end component; + +component pc is port ( + clk: in std_logic; + rst: in std_logic; + ipc: in std_logic_vector(31 downto 0); + opc: out std_logic_vector(31 downto 0) +); +end component; + +constant c_pc_add_val: std_logic_vector(31 downto 0) := x"00000004"; +signal s_adder_out: std_logic_vector(31 downto 0); +signal s_pc_out: std_logic_vector(31 downto 0); +signal s_alu_out: std_logic_vector(31 downto 0); +signal s_reg_dst: std_logic; +signal s_reg_wr: std_logic; +signal s_alu_src: std_logic; +signal s_branch: std_logic; +signal s_mem_rd: std_logic; +signal s_mem_wr: std_logic; +signal s_mem_toreg: std_logic; +signal s_alu_op: std_logic_vector(1 downto 0); +signal s_op: std_logic_vector(3 downto 0); +signal s_reg_out1: std_logic_vector(31 downto 0); +signal s_reg_out2: std_logic_vector(31 downto 0); +signal s_alu_zero: std_logic; +signal s_instr: std_logic_vector(31 downto 0); + +begin + alu_map: alu port map ( + alu_in1 => s_reg_out1, + alu_in2 => s_reg_out2, + alu_ctrl => s_op, + alu_out => s_alu_out, + alu_zero => s_alu_zero + ); + + regfile_ext_map: regfile_ext port map ( + idata => s_alu_out, + raddr1 => s_instr(25 downto 21), + raddr2 => s_instr(20 downto 16), + waddr => s_instr(15 downto 11), + we => s_reg_wr, + clk => m_clk, + rst => m_rst, + odata1 => s_reg_out1, + odata2 => s_reg_out2 + ); + + instrmem_map: instrmem port map ( + addr => s_pc_out, + c => s_instr + ); + + ctrl_map: ctrl port map ( + funct => s_instr(31 downto 26), + reg_dst => s_reg_dst, + reg_wr => s_reg_wr, + alu_src => s_alu_src, + branch => s_branch, + mem_rd => s_mem_rd, + mem_wr => s_mem_wr, + mem_toreg => s_mem_toreg, + alu_op => s_alu_op + ); + + alu_ctrl_map: alu_ctrl port map ( + funct => s_instr(5 downto 0), + alu_op => s_alu_op, + op => s_op + ); + + adder32_map: adder32 port map ( + x => s_pc_out, + y => c_pc_add_val, + z => s_adder_out + ); + + pc_map: pc port map ( + clk => m_clk, + rst => m_rst, + ipc => s_adder_out, + opc => s_pc_out + ); +end struct; diff --git a/vhdl_digital_design/project/part7_mips_r_ops/mips_tb.vhd b/vhdl_digital_design/project/part7_mips_r_ops/mips_tb.vhd @@ -0,0 +1,55 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity mips_tb is +end mips_tb; + +architecture behav of mips_tb is + +signal s_m_clk: std_logic; +signal s_m_rst: std_logic; + +component mips is port ( + m_clk: in std_logic; + m_rst: in std_logic +); +end component; + +begin + uut: mips port map ( + m_clk => s_m_clk, + m_rst => s_m_rst, + ); + + process begin + -- Reset everything. + s_m_rst <= '1'; + s_m_clk <= '0'; + wait for 250 ns; + + s_m_clk <= '1'; + wait for 250 ns; + + -- 1st cycle. + s_m_rst <= '0'; + s_m_clk <= '0'; + wait for 250 ns; + + s_m_clk <= '1'; + wait for 250 ns; + + -- 2nd cycle. + s_m_clk <= '0'; + wait for 250 ns; + + s_m_clk <= '1'; + wait for 250 ns; + + -- 3rd cycle. + s_m_clk <= '0'; + wait for 250 ns; + + s_m_clk <= '1'; + wait for 250 ns; + end process; +end behav; diff --git a/vhdl_digital_design/project/part7_mips_r_ops/pc.vhd b/vhdl_digital_design/project/part7_mips_r_ops/pc.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity pc is port ( + clk: in std_logic; + rst: in std_logic; + ipc: in std_logic_vector(31 downto 0); + opc: out std_logic_vector(31 downto 0) +); +end pc; + +architecture behav of pc is +begin + process (clk, rst) begin + if (rst = '1') then + opc <= x"00000000"; + elsif (clk'event and clk = '0') then + opc <= ipc; + end if; + end process; +end behav; diff --git a/vhdl_digital_design/project/part6_mips_r_ops/regfile_ext.vhd b/vhdl_digital_design/project/part7_mips_r_ops/regfile_ext.vhd